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[PULL 01/12] riscv: Convert interrupt logs to use qemu_log_mask()
From: |
Alistair Francis |
Subject: |
[PULL 01/12] riscv: Convert interrupt logs to use qemu_log_mask() |
Date: |
Fri, 23 Oct 2020 08:16:08 -0700 |
Currently we log interrupts and exceptions using the trace backend in
riscv_cpu_do_interrupt(). We also log exceptions using the interrupt log
mask (-d int) in riscv_raise_exception().
This patch converts riscv_cpu_do_interrupt() to log both interrupts and
exceptions with the interrupt log mask, so that both are printed when a
user runs QEMU with -d int.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id:
29a8c766c7c4748d0f2711c3a0abb81208138c5e.1601652179.git.alistair.francis@wdc.com
---
target/riscv/cpu_helper.c | 8 +++++++-
target/riscv/op_helper.c | 1 -
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 904899054d..6c68239a46 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -895,7 +895,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
}
trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
- riscv_cpu_get_trap_name(cause, async));
+ riscv_cpu_get_trap_name(cause, async));
+
+ qemu_log_mask(CPU_LOG_INT,
+ "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", "
+ "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n",
+ __func__, env->mhartid, async, cause, env->pc, tval,
+ riscv_cpu_get_trap_name(cause, async));
if (env->priv <= PRV_S &&
cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 9b9ada45a9..e987bd262f 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -29,7 +29,6 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
uint32_t exception, uintptr_t pc)
{
CPUState *cs = env_cpu(env);
- qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception);
cs->exception_index = exception;
cpu_loop_exit_restore(cs, pc);
}
--
2.28.0
- [PULL 00/12] riscv-to-apply queue, Alistair Francis, 2020/10/23
- [PULL 01/12] riscv: Convert interrupt logs to use qemu_log_mask(),
Alistair Francis <=
- [PULL 03/12] target/riscv: Fix update of hstatus.SPVP, Alistair Francis, 2020/10/23
- [PULL 02/12] hw/intc: Move sifive_plic.h to the include directory, Alistair Francis, 2020/10/23
- [PULL 05/12] target/riscv: Fix implementation of HLVX.WU instruction, Alistair Francis, 2020/10/23
- [PULL 06/12] hw/riscv: sifive_u: Allow specifying the CPU, Alistair Francis, 2020/10/23
- [PULL 08/12] hw/riscv: Add a riscv_is_32_bit() function, Alistair Francis, 2020/10/23
- [PULL 07/12] hw/riscv: Return the end address of the loaded firmware, Alistair Francis, 2020/10/23
- [PULL 09/12] hw/riscv: Load the kernel after the firmware, Alistair Francis, 2020/10/23
- [PULL 10/12] target/riscv: raise exception to HS-mode at get_physical_address, Alistair Francis, 2020/10/23
- [PULL 11/12] hw/misc/sifive_u_otp: Add write function and write-once protection, Alistair Francis, 2020/10/23
- [PULL 04/12] target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt, Alistair Francis, 2020/10/23