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Re: [PULL 00/12] riscv-to-apply queue
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From: |
Peter Maydell |
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Subject: |
Re: [PULL 00/12] riscv-to-apply queue |
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Date: |
Mon, 26 Oct 2020 13:16:14 +0000 |
On Fri, 23 Oct 2020 at 16:27, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 4c5b97bfd0dd54dc27717ae8d1cd10e14eef1430:
>
> Merge remote-tracking branch
> 'remotes/kraxel/tags/modules-20201022-pull-request' into staging (2020-10-22
> 12:33:21 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201023
>
> for you to fetch changes up to 51b6c1bbc3dd1b139a9e9b021d87bcfd7d82299e:
>
> hw/misc/sifive_u_otp: Add backend drive support (2020-10-22 12:00:50 -0700)
>
> ----------------------------------------------------------------
> A collection of RISC-V fixes for the next QEMU release.
>
> This includes:
> - Improvements to logging output
> - Hypervisor instruction fixups
> - The ability to load a noMMU kernel
> - SiFive OTP support
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.
-- PMM
- [PULL 02/12] hw/intc: Move sifive_plic.h to the include directory, (continued)
- [PULL 02/12] hw/intc: Move sifive_plic.h to the include directory, Alistair Francis, 2020/10/23
- [PULL 05/12] target/riscv: Fix implementation of HLVX.WU instruction, Alistair Francis, 2020/10/23
- [PULL 06/12] hw/riscv: sifive_u: Allow specifying the CPU, Alistair Francis, 2020/10/23
- [PULL 08/12] hw/riscv: Add a riscv_is_32_bit() function, Alistair Francis, 2020/10/23
- [PULL 07/12] hw/riscv: Return the end address of the loaded firmware, Alistair Francis, 2020/10/23
- [PULL 09/12] hw/riscv: Load the kernel after the firmware, Alistair Francis, 2020/10/23
- [PULL 10/12] target/riscv: raise exception to HS-mode at get_physical_address, Alistair Francis, 2020/10/23
- [PULL 11/12] hw/misc/sifive_u_otp: Add write function and write-once protection, Alistair Francis, 2020/10/23
- [PULL 04/12] target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt, Alistair Francis, 2020/10/23
- [PULL 12/12] hw/misc/sifive_u_otp: Add backend drive support, Alistair Francis, 2020/10/23
- Re: [PULL 00/12] riscv-to-apply queue,
Peter Maydell <=