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[PULL 06/18] target/arm: Fix sve ldr/str
From: |
Peter Maydell |
Subject: |
[PULL 06/18] target/arm: Fix sve ldr/str |
Date: |
Thu, 1 Oct 2020 15:47:47 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
The mte update missed a bit when producing clean addresses.
Fixes: b2aa8879b88
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200916014102.2446323-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-sve.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index e4cd6b62517..c0d8a5863a2 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4290,7 +4290,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int
len, int rn, int imm)
for (i = 0; i < len_align; i += 8) {
tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ);
tcg_gen_st_i64(t0, cpu_env, vofs + i);
- tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8);
+ tcg_gen_addi_i64(clean_addr, clean_addr, 8);
}
tcg_temp_free_i64(t0);
} else {
@@ -4379,7 +4379,7 @@ static void do_str(DisasContext *s, uint32_t vofs, int
len, int rn, int imm)
for (i = 0; i < len_align; i += 8) {
tcg_gen_ld_i64(t0, cpu_env, vofs + i);
tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEQ);
- tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8);
+ tcg_gen_addi_i64(clean_addr, clean_addr, 8);
}
tcg_temp_free_i64(t0);
} else {
--
2.20.1
- [PULL 00/18] target-arm queue, Peter Maydell, 2020/10/01
- [PULL 01/18] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check, Peter Maydell, 2020/10/01
- [PULL 02/18] target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters, Peter Maydell, 2020/10/01
- [PULL 04/18] target/arm: Add ID register values for Cortex-M0, Peter Maydell, 2020/10/01
- [PULL 03/18] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs, Peter Maydell, 2020/10/01
- [PULL 06/18] target/arm: Fix sve ldr/str,
Peter Maydell <=
- [PULL 05/18] target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile, Peter Maydell, 2020/10/01
- [PULL 07/18] target/arm: Fix SVE splice, Peter Maydell, 2020/10/01
- [PULL 08/18] hw/arm/raspi: Define various blocks base addresses, Peter Maydell, 2020/10/01
- [PULL 09/18] hw/arm/bcm2835: Add more unimplemented peripherals, Peter Maydell, 2020/10/01
- [PULL 10/18] hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2, Peter Maydell, 2020/10/01
- [PULL 11/18] hw/arm/raspi: Display the board revision in the machine description, Peter Maydell, 2020/10/01
- [PULL 13/18] hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState, Peter Maydell, 2020/10/01
- [PULL 12/18] hw/arm/raspi: Load the firmware on the first core, Peter Maydell, 2020/10/01
- [PULL 15/18] hw/arm/raspi: Use more specific machine names, Peter Maydell, 2020/10/01
- [PULL 14/18] hw/arm/raspi: Avoid using TypeInfo::class_data pointer, Peter Maydell, 2020/10/01