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[PULL 04/18] target/arm: Add ID register values for Cortex-M0
From: |
Peter Maydell |
Subject: |
[PULL 04/18] target/arm: Add ID register values for Cortex-M0 |
Date: |
Thu, 1 Oct 2020 15:47:45 +0100 |
Give the Cortex-M0 ID register values corresponding to its
implemented behaviour. These will not be guest-visible but will be
used to govern the behaviour of QEMU's emulation. We use the same
values that the Cortex-M3 does.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-5-peter.maydell@linaro.org
---
target/arm/cpu_tcg.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index a9b7cf52550..0013e25412f 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -256,6 +256,30 @@ static void cortex_m0_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_M);
cpu->midr = 0x410cc200;
+
+ /*
+ * These ID register values are not guest visible, because
+ * we do not implement the Main Extension. They must be set
+ * to values corresponding to the Cortex-M0's implemented
+ * features, because QEMU generally controls its emulation
+ * by looking at ID register fields. We use the same values as
+ * for the M3.
+ */
+ cpu->isar.id_pfr0 = 0x00000030;
+ cpu->isar.id_pfr1 = 0x00000200;
+ cpu->isar.id_dfr0 = 0x00100000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00000030;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x00000000;
+ cpu->isar.id_mmfr3 = 0x00000000;
+ cpu->isar.id_isar0 = 0x01141110;
+ cpu->isar.id_isar1 = 0x02111000;
+ cpu->isar.id_isar2 = 0x21112231;
+ cpu->isar.id_isar3 = 0x01111110;
+ cpu->isar.id_isar4 = 0x01310102;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
}
static void cortex_m3_initfn(Object *obj)
--
2.20.1
- [PULL 00/18] target-arm queue, Peter Maydell, 2020/10/01
- [PULL 01/18] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check, Peter Maydell, 2020/10/01
- [PULL 02/18] target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters, Peter Maydell, 2020/10/01
- [PULL 04/18] target/arm: Add ID register values for Cortex-M0,
Peter Maydell <=
- [PULL 03/18] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs, Peter Maydell, 2020/10/01
- [PULL 06/18] target/arm: Fix sve ldr/str, Peter Maydell, 2020/10/01
- [PULL 05/18] target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile, Peter Maydell, 2020/10/01
- [PULL 07/18] target/arm: Fix SVE splice, Peter Maydell, 2020/10/01
- [PULL 08/18] hw/arm/raspi: Define various blocks base addresses, Peter Maydell, 2020/10/01
- [PULL 09/18] hw/arm/bcm2835: Add more unimplemented peripherals, Peter Maydell, 2020/10/01
- [PULL 10/18] hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2, Peter Maydell, 2020/10/01
- [PULL 11/18] hw/arm/raspi: Display the board revision in the machine description, Peter Maydell, 2020/10/01
- [PULL 13/18] hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState, Peter Maydell, 2020/10/01
- [PULL 12/18] hw/arm/raspi: Load the firmware on the first core, Peter Maydell, 2020/10/01