[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 03/18] hw/intc/armv7m_nvic: Only show ID register values for Main
From: |
Peter Maydell |
Subject: |
[PULL 03/18] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs |
Date: |
Thu, 1 Oct 2020 15:47:44 +0100 |
M-profile CPUs only implement the ID registers as guest-visible if
the CPU implements the Main Extension (all our current CPUs except
the Cortex-M0 do).
Currently we handle this by having the Cortex-M0 leave the ID
register values in the ARMCPU struct as zero, but this conflicts with
our design decision to make QEMU behaviour be keyed off ID register
fields wherever possible.
Explicitly code the ID registers in the NVIC to return 0 if the Main
Extension is not implemented, so we can make the M0 model set the
ARMCPU struct fields to obtain the correct behaviour without those
values becoming guest-visible.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-4-peter.maydell@linaro.org
---
hw/intc/armv7m_nvic.c | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index a28be49c1e9..42b1ad59e65 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1238,32 +1238,74 @@ static uint32_t nvic_readl(NVICState *s, uint32_t
offset, MemTxAttrs attrs)
"Aux Fault status registers unimplemented\n");
return 0;
case 0xd40: /* PFR0. */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+ goto bad_offset;
+ }
return cpu->isar.id_pfr0;
case 0xd44: /* PFR1. */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+ goto bad_offset;
+ }
return cpu->isar.id_pfr1;
case 0xd48: /* DFR0. */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+ goto bad_offset;
+ }
return cpu->isar.id_dfr0;
case 0xd4c: /* AFR0. */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+ goto bad_offset;
+ }
return cpu->id_afr0;
case 0xd50: /* MMFR0. */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+ goto bad_offset;
+ }
return cpu->isar.id_mmfr0;
case 0xd54: /* MMFR1. */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+ goto bad_offset;
+ }
return cpu->isar.id_mmfr1;
case 0xd58: /* MMFR2. */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+ goto bad_offset;
+ }
return cpu->isar.id_mmfr2;
case 0xd5c: /* MMFR3. */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+ goto bad_offset;
+ }
return cpu->isar.id_mmfr3;
case 0xd60: /* ISAR0. */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+ goto bad_offset;
+ }
return cpu->isar.id_isar0;
case 0xd64: /* ISAR1. */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+ goto bad_offset;
+ }
return cpu->isar.id_isar1;
case 0xd68: /* ISAR2. */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+ goto bad_offset;
+ }
return cpu->isar.id_isar2;
case 0xd6c: /* ISAR3. */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+ goto bad_offset;
+ }
return cpu->isar.id_isar3;
case 0xd70: /* ISAR4. */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+ goto bad_offset;
+ }
return cpu->isar.id_isar4;
case 0xd74: /* ISAR5. */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+ goto bad_offset;
+ }
return cpu->isar.id_isar5;
case 0xd78: /* CLIDR */
return cpu->clidr;
--
2.20.1
- [PULL 00/18] target-arm queue, Peter Maydell, 2020/10/01
- [PULL 01/18] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check, Peter Maydell, 2020/10/01
- [PULL 02/18] target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters, Peter Maydell, 2020/10/01
- [PULL 04/18] target/arm: Add ID register values for Cortex-M0, Peter Maydell, 2020/10/01
- [PULL 03/18] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs,
Peter Maydell <=
- [PULL 06/18] target/arm: Fix sve ldr/str, Peter Maydell, 2020/10/01
- [PULL 05/18] target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile, Peter Maydell, 2020/10/01
- [PULL 07/18] target/arm: Fix SVE splice, Peter Maydell, 2020/10/01
- [PULL 08/18] hw/arm/raspi: Define various blocks base addresses, Peter Maydell, 2020/10/01
- [PULL 09/18] hw/arm/bcm2835: Add more unimplemented peripherals, Peter Maydell, 2020/10/01
- [PULL 10/18] hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2, Peter Maydell, 2020/10/01
- [PULL 11/18] hw/arm/raspi: Display the board revision in the machine description, Peter Maydell, 2020/10/01
- [PULL 13/18] hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState, Peter Maydell, 2020/10/01
- [PULL 12/18] hw/arm/raspi: Load the firmware on the first core, Peter Maydell, 2020/10/01
- [PULL 15/18] hw/arm/raspi: Use more specific machine names, Peter Maydell, 2020/10/01