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[PULL 27/29] target/arm: Allow user-mode code to write CPSR.E via MSR
From: |
Peter Maydell |
Subject: |
[PULL 27/29] target/arm: Allow user-mode code to write CPSR.E via MSR |
Date: |
Thu, 21 May 2020 20:16:08 +0100 |
Using the MSR instruction to write to CPSR.E is deprecated, but it is
required to work from any mode including unprivileged code. We were
incorrectly forbidding usermode code from writing it because
CPSR_USER did not include the CPSR_E bit.
We use CPSR_USER in only three places:
* as the mask of what to allow userspace MSR to write to CPSR
* when deciding what bits a linux-user signal-return should be
able to write from the sigcontext structure
* in target_user_copy_regs() when we set up the initial
registers for the linux-user process
In the first two cases not being able to update CPSR.E is a bug, and
in the third case it doesn't matter because CPSR.E is always 0 there.
So we can fix both bugs by adding CPSR_E to CPSR_USER.
Because the cpsr_write() in restore_sigcontext() is now changing
a CPSR bit which is cached in hflags, we need to add an
arm_rebuild_hflags() call there; the callsite in
target_user_copy_regs() was already rebuilding hflags for other
reasons.
(The recommended way to change CPSR.E is to use the 'SETEND'
instruction, which we do correctly allow from usermode code.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.h | 2 +-
linux-user/arm/signal.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5d995368d4f..677584e5da0 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1230,7 +1230,7 @@ void pmu_init(ARMCPU *cpu);
#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
| CPSR_NZCV)
/* Bits writable in user mode. */
-#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
+#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
/* Execution state bits. MRS read as zero, MSR writes ignored. */
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
index d96fc27ce11..8020c80acb5 100644
--- a/linux-user/arm/signal.c
+++ b/linux-user/arm/signal.c
@@ -546,6 +546,7 @@ restore_sigcontext(CPUARMState *env, struct
target_sigcontext *sc)
#ifdef TARGET_CONFIG_CPU_32
__get_user(cpsr, &sc->arm_cpsr);
cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
+ arm_rebuild_hflags(env);
#endif
err |= !valid_user_regs(env);
--
2.20.1
- [PULL 17/29] hw/arm/fsl-imx6ul: Connect watchdog interrupts, (continued)
- [PULL 17/29] hw/arm/fsl-imx6ul: Connect watchdog interrupts, Peter Maydell, 2020/05/21
- [PULL 18/29] hw/arm/fsl-imx7: Instantiate various unimplemented devices, Peter Maydell, 2020/05/21
- [PULL 19/29] hw/arm/fsl-imx7: Connect watchdog interrupts, Peter Maydell, 2020/05/21
- [PULL 20/29] hw/arm/integratorcp: Replace hw_error() by qemu_log_mask(), Peter Maydell, 2020/05/21
- [PULL 21/29] hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask(), Peter Maydell, 2020/05/21
- [PULL 22/29] hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask(), Peter Maydell, 2020/05/21
- [PULL 23/29] hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask(), Peter Maydell, 2020/05/21
- [PULL 25/29] target/arm: Use tcg_gen_gvec_mov for clear_vec_high, Peter Maydell, 2020/05/21
- [PULL 24/29] ARM: PL061: Introduce N_GPIOS, Peter Maydell, 2020/05/21
- [PULL 26/29] target/arm: Use clear_vec_high more effectively, Peter Maydell, 2020/05/21
- [PULL 27/29] target/arm: Allow user-mode code to write CPSR.E via MSR,
Peter Maydell <=
- [PULL 28/29] linux-user/arm: Reset CPSR_E when entering a signal handler, Peter Maydell, 2020/05/21
- [PULL 29/29] linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32, Peter Maydell, 2020/05/21