[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 23/29] hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mas
From: |
Peter Maydell |
Subject: |
[PULL 23/29] hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask() |
Date: |
Thu, 21 May 2020 20:16:04 +0100 |
From: Philippe Mathieu-Daudé <address@hidden>
hw_error() calls exit(). This a bit overkill when we can log
the accesses as unimplemented or guest error.
When fuzzing the devices, we don't want the whole process to
exit. Replace some hw_error() calls by qemu_log_mask().
Per the datasheet "Exynos 4412 RISC Microprocessor Rev 1.00"
Chapter 25 "Multi Core Timer (MCT)" figure 1 and table 4,
the default value on the APB bus is 0.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/timer/exynos4210_mct.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
index 570cf7075bc..29a4b10676a 100644
--- a/hw/timer/exynos4210_mct.c
+++ b/hw/timer/exynos4210_mct.c
@@ -54,7 +54,6 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
-#include "hw/hw.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qemu/timer.h"
@@ -62,7 +61,6 @@
#include "hw/ptimer.h"
#include "hw/arm/exynos4210.h"
-#include "hw/hw.h"
#include "hw/irq.h"
//#define DEBUG_MCT
@@ -1062,7 +1060,7 @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr
offset,
int index;
int shift;
uint64_t count;
- uint32_t value;
+ uint32_t value = 0;
int lt_i;
switch (offset) {
@@ -1158,8 +1156,8 @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr
offset,
break;
default:
- hw_error("exynos4210.mct: bad read offset "
- TARGET_FMT_plx "\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
+ __func__, offset);
break;
}
return value;
@@ -1484,8 +1482,8 @@ static void exynos4210_mct_write(void *opaque, hwaddr
offset,
break;
default:
- hw_error("exynos4210.mct: bad write offset "
- TARGET_FMT_plx "\n", offset);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
+ __func__, offset);
break;
}
}
--
2.20.1
- [PULL 13/29] hw/watchdog: Implement full i.MX watchdog support, (continued)
- [PULL 13/29] hw/watchdog: Implement full i.MX watchdog support, Peter Maydell, 2020/05/21
- [PULL 14/29] hw/arm/fsl-imx25: Wire up watchdog, Peter Maydell, 2020/05/21
- [PULL 15/29] hw/arm/fsl-imx31: Wire up watchdog, Peter Maydell, 2020/05/21
- [PULL 16/29] hw/arm/fsl-imx6: Connect watchdog interrupts, Peter Maydell, 2020/05/21
- [PULL 17/29] hw/arm/fsl-imx6ul: Connect watchdog interrupts, Peter Maydell, 2020/05/21
- [PULL 18/29] hw/arm/fsl-imx7: Instantiate various unimplemented devices, Peter Maydell, 2020/05/21
- [PULL 19/29] hw/arm/fsl-imx7: Connect watchdog interrupts, Peter Maydell, 2020/05/21
- [PULL 20/29] hw/arm/integratorcp: Replace hw_error() by qemu_log_mask(), Peter Maydell, 2020/05/21
- [PULL 21/29] hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask(), Peter Maydell, 2020/05/21
- [PULL 22/29] hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask(), Peter Maydell, 2020/05/21
- [PULL 23/29] hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask(),
Peter Maydell <=
- [PULL 25/29] target/arm: Use tcg_gen_gvec_mov for clear_vec_high, Peter Maydell, 2020/05/21
- [PULL 24/29] ARM: PL061: Introduce N_GPIOS, Peter Maydell, 2020/05/21
- [PULL 26/29] target/arm: Use clear_vec_high more effectively, Peter Maydell, 2020/05/21
- [PULL 27/29] target/arm: Allow user-mode code to write CPSR.E via MSR, Peter Maydell, 2020/05/21
- [PULL 28/29] linux-user/arm: Reset CPSR_E when entering a signal handler, Peter Maydell, 2020/05/21
- [PULL 29/29] linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32, Peter Maydell, 2020/05/21