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[PULL 07/39] target/arm: Use correct variable for setting 'max' cpu's ID
From: |
Peter Maydell |
Subject: |
[PULL 07/39] target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0 |
Date: |
Mon, 4 May 2020 13:32:37 +0100 |
In aarch64_max_initfn() we update both 32-bit and 64-bit ID
registers. The intended pattern is that for 64-bit ID registers we
use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID
registers use FIELD_DP32 and the uint32_t 'u' register. For
ID_AA64DFR0 we accidentally used 'u', meaning that the top 32 bits of
this 64-bit ID register would end up always zero. Luckily at the
moment that's what they should be anyway, so this bug has no visible
effects.
Use the right-sized variable.
Fixes: 3bec78447a958d481991
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
---
target/arm/cpu64.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index e232c0ea12c..9bdf75b1abb 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -710,9 +710,9 @@ static void aarch64_max_initfn(Object *obj)
u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
cpu->isar.id_mmfr4 = u;
- u = cpu->isar.id_aa64dfr0;
- u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
- cpu->isar.id_aa64dfr0 = u;
+ t = cpu->isar.id_aa64dfr0;
+ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
+ cpu->isar.id_aa64dfr0 = t;
u = cpu->isar.id_dfr0;
u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
--
2.20.1
- [PULL 00/39] target-arm queue, Peter Maydell, 2020/05/04
- [PULL 01/39] target/arm: Make VQDMULL undefined when U=1, Peter Maydell, 2020/05/04
- [PULL 02/39] hw/arm/mps2-tz: Use TYPE_IOTKIT instead of hardcoded string, Peter Maydell, 2020/05/04
- [PULL 05/39] target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae(), Peter Maydell, 2020/05/04
- [PULL 06/39] target/arm: Implement ARMv8.2-TTS2UXN, Peter Maydell, 2020/05/04
- [PULL 03/39] target/arm: Don't use a TLB for ARMMMUIdx_Stage2, Peter Maydell, 2020/05/04
- [PULL 04/39] target/arm: Use enum constant in get_phys_addr_lpae() call, Peter Maydell, 2020/05/04
- [PULL 08/39] target/arm: Use uint64_t for midr field in CPU state struct, Peter Maydell, 2020/05/04
- [PULL 07/39] target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0,
Peter Maydell <=
- [PULL 11/39] hw/arm: versal-virt: Fix typo xlnx-ve -> xlnx-versal, Peter Maydell, 2020/05/04
- [PULL 09/39] hw/arm: versal: Remove inclusion of arm_gicv3_common.h, Peter Maydell, 2020/05/04
- [PULL 10/39] hw/arm: versal: Move misplaced comment, Peter Maydell, 2020/05/04
- [PULL 12/39] hw/arm: versal: Embed the UARTs into the SoC type, Peter Maydell, 2020/05/04
- [PULL 13/39] hw/arm: versal: Embed the GEMs into the SoC type, Peter Maydell, 2020/05/04
- [PULL 14/39] hw/arm: versal: Embed the ADMAs into the SoC type, Peter Maydell, 2020/05/04
- [PULL 15/39] hw/arm: versal: Embed the APUs into the SoC type, Peter Maydell, 2020/05/04
- [PULL 16/39] hw/arm: versal: Add support for SD, Peter Maydell, 2020/05/04
- [PULL 17/39] hw/arm: versal: Add support for the RTC, Peter Maydell, 2020/05/04
- [PULL 19/39] hw/arm: versal-virt: Add support for the RTC, Peter Maydell, 2020/05/04