Re: [Qemu-devel] [PATCH v2 15/68] target/arm: Convert BX, BXJ, BLX (register)

[Richard Henderson]

On 8/23/19 4:49 AM, Peter Maydell wrote:
> On Mon, 19 Aug 2019 at 22:38, Richard Henderson
> <address@hidden> wrote:
>>
>> Signed-off-by: Richard Henderson <address@hidden>
>> ---
>>  target/arm/translate.c | 78 ++++++++++++++++++++----------------------
>>  target/arm/a32.decode  |  7 ++++
>>  target/arm/t32.decode  |  2 ++
>>  3 files changed, 47 insertions(+), 40 deletions(-)
> 
>> @@ -195,8 +196,14 @@ CRC32CW          .... 0001 0100 .... .... 0010 0100 
>> ....      @rndm
>>
>>  %sysm            8:1 16:4
>>
>> +@rm              ---- .... .... .... .... .... .... rm:4      &r
>> +
>>  MRS_bank         ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000  &mrs_bank 
>> %sysm
>>  MSR_bank         ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4  &msr_bank 
>> %sysm
>>
>>  MRS_reg          ---- 0001 0 r:1 00 1111   rd:4 0000 0000 0000  &mrs_reg
>>  MSR_reg          ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4  &msr_reg
>> +
>> +BX               .... 0001 0010 1111 1111 1111 0001 ....      @rm
>> +BXJ              .... 0001 0010 1111 1111 1111 0010 ....      @rm
>> +BLX_r            .... 0001 0010 1111 1111 1111 0011 ....      @rm
> 
> Why do the decode patterns for these use '....' in the cond field
> rather than '----' like the other patterns ?

As much as possible I've tried to put the "----" in the format, so that it'll
be easier in future to add a cond:4 field.  Except that the MRS/MSR insns are
all one-offs so I didn't bother creating a separate format.


r~

> 
> Otherwise
> Reviewed-by: Peter Maydell <address@hidden>
> 
> thanks
> -- PMM
>