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Re: [Qemu-devel] [PATCH v2 15/68] target/arm: Convert BX, BXJ, BLX (regi
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 15/68] target/arm: Convert BX, BXJ, BLX (register) |
Date: |
Fri, 23 Aug 2019 12:49:40 +0100 |
On Mon, 19 Aug 2019 at 22:38, Richard Henderson
<address@hidden> wrote:
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/arm/translate.c | 78 ++++++++++++++++++++----------------------
> target/arm/a32.decode | 7 ++++
> target/arm/t32.decode | 2 ++
> 3 files changed, 47 insertions(+), 40 deletions(-)
> @@ -195,8 +196,14 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 ....
> @rndm
>
> %sysm 8:1 16:4
>
> +@rm ---- .... .... .... .... .... .... rm:4 &r
> +
> MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm
> MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm
>
> MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg
> MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg
> +
> +BX .... 0001 0010 1111 1111 1111 0001 .... @rm
> +BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm
> +BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm
Why do the decode patterns for these use '....' in the cond field
rather than '----' like the other patterns ?
Otherwise
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- Re: [Qemu-devel] [PATCH v2 10/68] target/arm: Simplify op_smlaxxx for SMLAL*, (continued)
- [Qemu-devel] [PATCH v2 09/68] target/arm: Convert Halfword multiply and multiply accumulate, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 12/68] target/arm: Convert MSR (immediate) and hints, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 11/68] target/arm: Simplify op_smlawx for SMLAW*, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 13/68] target/arm: Convert MRS/MSR (banked, register), Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 15/68] target/arm: Convert BX, BXJ, BLX (register), Richard Henderson, 2019/08/19
- Re: [Qemu-devel] [PATCH v2 15/68] target/arm: Convert BX, BXJ, BLX (register),
Peter Maydell <=
- [Qemu-devel] [PATCH v2 17/68] target/arm: Convert ERET, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 14/68] target/arm: Convert Cyclic Redundancy Check, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 18/68] target/arm: Convert the rest of A32 Miscelaneous instructions, Richard Henderson, 2019/08/19