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Re: [Qemu-devel] [PATCH v2 11/68] target/arm: Simplify op_smlawx for SML
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 11/68] target/arm: Simplify op_smlawx for SMLAW* |
Date: |
Fri, 23 Aug 2019 13:21:55 +0100 |
On Mon, 19 Aug 2019 at 22:38, Richard Henderson
<address@hidden> wrote:
>
> By shifting the 16-bit input left by 16, we can align the desired
> portion of the 48-bit product and use tcg_gen_muls2_i32.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/arm/translate.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- Re: [Qemu-devel] [PATCH v2 08/68] target/arm: Convert Saturating addition and subtraction, (continued)
- [Qemu-devel] [PATCH v2 05/68] target/arm: Convert Data Processing (immediate), Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 10/68] target/arm: Simplify op_smlaxxx for SMLAL*, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 09/68] target/arm: Convert Halfword multiply and multiply accumulate, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 12/68] target/arm: Convert MSR (immediate) and hints, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 11/68] target/arm: Simplify op_smlawx for SMLAW*, Richard Henderson, 2019/08/19
- Re: [Qemu-devel] [PATCH v2 11/68] target/arm: Simplify op_smlawx for SMLAW*,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 13/68] target/arm: Convert MRS/MSR (banked, register), Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 15/68] target/arm: Convert BX, BXJ, BLX (register), Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 17/68] target/arm: Convert ERET, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 14/68] target/arm: Convert Cyclic Redundancy Check, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 18/68] target/arm: Convert the rest of A32 Miscelaneous instructions, Richard Henderson, 2019/08/19