[Qemu-devel] [Patch] ARM: Add an L2 cache controller to KZM

[Peter Chubb]

Reads to unassigned memory now return non-zero (since patch
9b8c69243585).  This breaks guests runnong on i.MX31 that use the
cache controller --- they poll forever waiting for the L2CC cache
invalidate regsiter to be zero.

This patch adds in an L2 cache controller.  It's not quite right ---
it reuses the PL2x0 implementation that  is already in QEMU.  The
differences however are minor --- a different ID, a different initial
value for the aux control register (because Freescale have used
some of the reserved bits), and the pl2x0 implements registers that
are not present in the Freescale cache controller.

Signed-off-by: Peter Chubb <address@hidden>

diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
index bd6c05c..018fc81 100644
--- a/hw/arm/kzm.c
+++ b/hw/arm/kzm.c
@@ -33,6 +33,7 @@
      * 0x1fffc000-0x1fffffff RAM                  EMULATED
      * 0x20000000-0x2fffffff Reserved             IGNORED
      * 0x30000000-0x7fffffff I.MX31 Internal Register Space
+     *   0x30000000-0x30000fff L2 Cache Controller PARTIALLY EMULATED
      *   0x43f00000 IO_AREA0
      *   0x43f90000 UART1                         EMULATED
      *   0x43f94000 UART2                         EMULATED
@@ -134,6 +135,15 @@ static void kzm_init(QEMUMachineInitArgs *args)
                        DEVICE_NATIVE_ENDIAN);
     }
 
+    /*
+     * The i.MX L2CC  is almost the same as the PL210
+     * except for a different ID (the implementor bits are different)
+     * and the `reserved' bits in the auxilliary control register
+     * are implemented.  The l2x0 qemu implementation is for a superset
+     * of the PL210.
+     */
+    sysbus_create_varargs("l2x0", 0x30000000, NULL);
+
     kzm_binfo.ram_size = ram_size;
     kzm_binfo.kernel_filename = kernel_filename;
     kzm_binfo.kernel_cmdline = kernel_cmdline;


--
Dr Peter Chubb                                  peter.chubb AT nicta.com.au
http://www.ssrg.nicta.com.au          Software Systems Research Group/NICTA