Re: [Qemu-devel] [PATCH for-1.6] target-mips: do not raise exceptions when accessing invalid memory

[Peter Maydell]

On 4 August 2013 23:04, Aurélien Jarno <address@hidden> wrote:
> The real hardware probably returns all 1 or all 0 for addresses not
> decoded to a device. This is what QEMU should model, and it should
> not trigger a DBE or IBE exception. Looking at the current MIPS
> documentation, Bus Error is defined as:
>
>   A bus error exception occurs when an instruction or data access makes a
>   bus request (due to a cache miss or an  uncacheable reference) and
>   that request terminates in an error.
>
> Older CPU documentation like the R4000 have a more precise definition:
>
>   A Bus Error exception is raised by board-level circuitry for events such
>   as bus time-out, backplane bus parity errors, and invalid physical memory
>   addresses or access types.
>
> As we don't model this kind of errors, we should definitely just not
> trigger an exception in that case, and even logging the event as
> unimplemented is probably wrong.

Well, we certainly can model invalid-physical-address and
bus-timeout where that's what the board does for accesses
to non-decoded addresses; but presumably in this case it
doesn't...

-- PMM