Re: [Qemu-devel] [Patch] ARM: Add an L2 cache controller to KZM

[Andreas Färber]

Am 06.08.2013 02:00, schrieb address@hidden:
>>>>>> "Andreas" == Andreas Färber <address@hidden> writes:
> 
> Andreas> Am 05.08.2013 11:18, schrieb Peter Maydell:
>>> On 5 August 2013 02:21, Peter Chubb <address@hidden>
>>> wrote:
>>>> Reads to unassigned memory now return non-zero (since patch
>>>> 9b8c69243585). This breaks guests runnong on i.MX31 that use the
>>>> cache controller --- they poll forever waiting for the L2CC cache
>>>> invalidate regsiter to be zero.
>>>
> Andreas> Peter Ch., if you know the exact differences, why don't you
> Andreas> just derive an imx-l2cc type (or so) derived from ARM's type,
> Andreas> overriding the values mentioned above? Sounds trivial to me.
> 
> Because I don't know how -- can you point me at some documentation?

There's no official how-to, but QOM is documented in include/qom/object.h.

May I simply point you to an example:
http://git.qemu.org/?p=qemu.git;a=commit;h=692a76d1c4a32573bf3cc19110c7fa6cc8c93f60

pl061 has Luminary and ARM IDs, with ARM in the base type and Luminary
overriding values. Another idea is to use an abstract base type and
several derived types if the differences are bigger.

Andreas

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