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Re: [PATCH 12/16] target/arm: Enable SCR and HCR bits for RAS
From: |
Peter Maydell |
Subject: |
Re: [PATCH 12/16] target/arm: Enable SCR and HCR bits for RAS |
Date: |
Mon, 11 Apr 2022 16:50:34 +0100 |
On Sat, 9 Apr 2022 at 01:11, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Enable writes to the TERR and TEA bits when RAS is enabled.
> These bits are otherwise RES0.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/helper.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- [PATCH 06/16] target/arm: Annotate arm_max_initfn with FEAT identifiers, (continued)
- [PATCH 06/16] target/arm: Annotate arm_max_initfn with FEAT identifiers, Richard Henderson, 2022/04/08
- [PATCH 08/16] target/arm: Enable FEAT_Debugv8p2 for -cpu max, Richard Henderson, 2022/04/08
- [PATCH 07/16] target/arm: Use field names for manipulating EL2 and EL3 modes, Richard Henderson, 2022/04/08
- [PATCH 09/16] target/arm: Enable FEAT_Debugv8p4 for -cpu max, Richard Henderson, 2022/04/08
- [PATCH 12/16] target/arm: Enable SCR and HCR bits for RAS, Richard Henderson, 2022/04/08
- Re: [PATCH 12/16] target/arm: Enable SCR and HCR bits for RAS,
Peter Maydell <=
- [PATCH 11/16] target/arm: Add minimal RAS registers, Richard Henderson, 2022/04/08
- [PATCH 14/16] target/arm: Implement ESB instruction, Richard Henderson, 2022/04/08
- [PATCH 15/16] target/arm: Enable FEAT_RAS for -cpu max, Richard Henderson, 2022/04/08