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[PATCH 15/16] target/arm: Enable FEAT_RAS for -cpu max
From: |
Richard Henderson |
Subject: |
[PATCH 15/16] target/arm: Enable FEAT_RAS for -cpu max |
Date: |
Fri, 8 Apr 2022 17:07:41 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu64.c | 1 +
target/arm/cpu_tcg.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f20fb6d9e1..03c6707111 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -801,6 +801,7 @@ static void aarch64_max_initfn(Object *obj)
t = cpu->isar.id_aa64pfr0;
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
+ t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index a443e8c48a..5cce9116d0 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -72,6 +72,7 @@ void arm32_max_features(ARMCPU *cpu)
t = cpu->isar.id_pfr0;
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
+ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
cpu->isar.id_pfr0 = t;
t = cpu->isar.id_pfr2;
--
2.25.1
- [PATCH 12/16] target/arm: Enable SCR and HCR bits for RAS, (continued)
[PATCH 15/16] target/arm: Enable FEAT_RAS for -cpu max,
Richard Henderson <=
[PATCH 10/16] target/arm: Add isar_feature_{aa64,any}_ras, Richard Henderson, 2022/04/08
[PATCH 13/16] target/arm: Implement virtual SError exceptions, Richard Henderson, 2022/04/08
[PATCH 16/16] target/arm: Enable FEAT_IESB for -cpu max, Richard Henderson, 2022/04/08