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Re: [PATCH 14/16] target/arm: Implement ESB instruction
From: |
Richard Henderson |
Subject: |
Re: [PATCH 14/16] target/arm: Implement ESB instruction |
Date: |
Mon, 11 Apr 2022 15:14:53 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 |
On 4/11/22 09:18, Peter Maydell wrote:
+ ESB ---- 0011 0010 0000 1111 ---- 0001 0000
+ ]
Why don't we decode bits [11:8] here? I see it's the same
as YIELD/WFE/WFI, but I'm not sure why we're not decoding
those bits in those insns either...
See page F4-7074 in H.a, where bits [11:8] of the imm12 field are described
with 'xxxx'.
+static bool trans_ESB(DisasContext *s, arg_ESB *a)
+{
+ if (dc_isar_feature(aa32_ras, s) &&
+ arm_dc_feature(s, ARM_FEATURE_EL2) &&
+ s->current_el <= 1) {
This is doing the right thing for M-profile but only rather
indirectly because it happens to get caught by the FEATURE_EL2
check.
Yes, I had though that a feature, reducing the number of checks, but...
I think it would be safer to explicitly check for
not-M-profile (which then gives you a place to put the
"For M-profile minimal-RAS ESB can be a NOP" comment that got
removed above).
... fair enough.
I think a comment noting that without RAS we must NOP would
be useful here.
Ok.
r~
- Re: [PATCH 07/16] target/arm: Use field names for manipulating EL2 and EL3 modes, (continued)
[PATCH 15/16] target/arm: Enable FEAT_RAS for -cpu max, Richard Henderson, 2022/04/08
[PATCH 10/16] target/arm: Add isar_feature_{aa64,any}_ras, Richard Henderson, 2022/04/08
[PATCH 13/16] target/arm: Implement virtual SError exceptions, Richard Henderson, 2022/04/08