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[PATCH 07/16] target/arm: Use field names for manipulating EL2 and EL3 m
From: |
Richard Henderson |
Subject: |
[PATCH 07/16] target/arm: Use field names for manipulating EL2 and EL3 modes |
Date: |
Fri, 8 Apr 2022 17:07:33 -0700 |
Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 22 +++++++++++++---------
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5d4ca7a227..6521f350f9 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1795,11 +1795,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
*/
unset_feature(env, ARM_FEATURE_EL3);
- /* Disable the security extension feature bits in the processor feature
- * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
+ /*
+ * Disable the security extension feature bits in the processor
+ * feature registers as well.
*/
- cpu->isar.id_pfr1 &= ~0xf0;
- cpu->isar.id_aa64pfr0 &= ~0xf000;
+ cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY,
0);
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+ ID_AA64PFR0, EL3, 0);
}
if (!cpu->has_el2) {
@@ -1830,12 +1832,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
}
if (!arm_feature(env, ARM_FEATURE_EL2)) {
- /* Disable the hypervisor feature bits in the processor feature
- * registers if we don't have EL2. These are id_pfr1[15:12] and
- * id_aa64pfr0_el1[11:8].
+ /*
+ * Disable the hypervisor feature bits in the processor feature
+ * registers if we don't have EL2.
*/
- cpu->isar.id_aa64pfr0 &= ~0xf00;
- cpu->isar.id_pfr1 &= ~0xf000;
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+ ID_AA64PFR0, EL2, 0);
+ cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
+ ID_PFR1, VIRTUALIZATION, 0);
}
#ifndef CONFIG_USER_ONLY
--
2.25.1
- [PATCH 03/16] target/arm: Update qemu-system-arm -cpu max to cortex-a57, (continued)
- [PATCH 03/16] target/arm: Update qemu-system-arm -cpu max to cortex-a57, Richard Henderson, 2022/04/08
- [PATCH 05/16] target/arm: Split out arm32_max_features, Richard Henderson, 2022/04/08
- [PATCH 06/16] target/arm: Annotate arm_max_initfn with FEAT identifiers, Richard Henderson, 2022/04/08
- [PATCH 08/16] target/arm: Enable FEAT_Debugv8p2 for -cpu max, Richard Henderson, 2022/04/08
- [PATCH 07/16] target/arm: Use field names for manipulating EL2 and EL3 modes,
Richard Henderson <=
- [PATCH 09/16] target/arm: Enable FEAT_Debugv8p4 for -cpu max, Richard Henderson, 2022/04/08
- [PATCH 12/16] target/arm: Enable SCR and HCR bits for RAS, Richard Henderson, 2022/04/08
- [PATCH 11/16] target/arm: Add minimal RAS registers, Richard Henderson, 2022/04/08
- [PATCH 14/16] target/arm: Implement ESB instruction, Richard Henderson, 2022/04/08