Re: [RFC] Adding the A64FX's HPC funtions.

[Richard Henderson]

On 6/1/21 8:21 AM, Peter Maydell wrote:
> > > I'm thinking of implementing A64FX HPC extension in qemu.
> > > A64FX [1] is a CPU developed by Fujitsu that implements armv8+SVE.
> > >
> > > [1]
> > > https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Microarchitecture
> > > _Manual_en_1.4.pdf
> > >
> > > A64FX is a CPU developed for HPC (High Performance Computing), and HPC
> > > extensions [2] are implemented to improve the performance of user programs.
> > >
> > > [2]
> > > https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Specification_HP
> > > C_Extension_v1_EN.pdf
> > >
> > > The details of each function are described in [2], and the HPC extensions
> > > include
> > > 1) Tag address override
> > > 2) Sector cache
> > > 3) Hardware barrier
> > > 4) Hardware prefetch assist
> > > are implemented.

Thanks for the pointers.  It looks to me that it'll be easy to implement these 
in qemu.  We'll need to implement the registers, so that the OS can read back 
the values, but we do not need to actually do anything with them.

> > > 1) Is target/arm/helper.c enough to implement the register (ARMCPRegInfo
> > > structure) of HPC extension function of A64FX?

Yes.

> > > 2) Is it OK to specify the option to set the HPC extension of A64FX as follows,
> > > for example?
> > >
> > > -M virt -cpu max,a64fx-hpc-sec=on (*sector cache function) -M virt -cpu
> > > max,a64fx-hpc-hwpf=on (*hardware prefetvh assist function) -M virt -cpu
> > > max,a64fx-hpc-hwb=on (*hardware barrier function)
> > >
> > > It is also possible to implement something like -cpu a64fx, but since we don't
> > > know if we can implement it immediately, we assume that we will use the -cpu
> > > max option first.

My first thought is that -cpu max can simply enable the extensions, without 
extra flags.  The max cpu has all of the features that we can enable, and as I 
see it this is just one more.

I would like to add -cpu a64fx at some point.  But as you say, that need not 
happen right away.

> > > Since there is no example of A64FX function implemented in QEMU, we would
> > > appreciate your comments before we post a patch.

We endeavor to enable features by the architectural id registers when possible. 
 Thus the cpu_isar_feature() checks in helper.c.

The microarchitectural document provided does not list all of the system 
register reset values for the A64FX, and I would be surprised if there were an 
architectural id register that specified a non-standard extension like this. 
Thus I would expect to add ARM_FEATURE_A64FX with which to enable these 
extensions in helper.c.

I can certainly help you with this.


r~