Re: [RFC] Adding the A64FX's HPC funtions.

[Peter Maydell]

It looks like you didn't get any responses because something went
wrong and your email never went out to the mailing lists.
I only got it because I was cc'd directly. I'll try effectively
resending it like this to see if that works better. You might want
to check whether the mail server at your end actually sent the
email or if you got a bounce mail or something.

thanks
-- PMM

On Tue, 1 Jun 2021 at 05:53, ishii.shuuichir@fujitsu.com
<ishii.shuuichir@fujitsu.com> wrote:
>
> Ping?
> I'd appreciate any comments.
>
> Best regards,
> Shuuichirou Ishii
>
> > -----Original Message-----
> > From: Ishii, Shuuichirou/石井 周一郎 <ishii.shuuichir@fujitsu.com>
> > Sent: Wednesday, May 26, 2021 4:57 PM
> > To: 'peter.maydell@linaro.org' <peter.maydell@linaro.org>;
> > 'qemu-arm@nongnu.org' <qemu-arm@nongnu.org>;
> > 'qemu-devel@nongnu.org' <qemu-devel@nongnu.org>
> > Cc: Ishii, Shuuichirou/石井 周一郎 <ishii.shuuichir@fujitsu.com>
> > Subject: [RFC] Adding the A64FX's HPC funtions.
> >
> > Hi all!
> >
> > I'm thinking of implementing A64FX HPC extension in qemu.
> > A64FX [1] is a CPU developed by Fujitsu that implements armv8+SVE.
> >
> > [1]
> > https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Microarchitecture
> > _Manual_en_1.4.pdf
> >
> > A64FX is a CPU developed for HPC (High Performance Computing), and HPC
> > extensions [2] are implemented to improve the performance of user programs.
> >
> > [2]
> > https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Specification_HP
> > C_Extension_v1_EN.pdf
> >
> > The details of each function are described in [2], and the HPC extensions
> > include
> > 1) Tag address override
> > 2) Sector cache
> > 3) Hardware barrier
> > 4) Hardware prefetch assist
> > are implemented.
> >
> > The A64FX has been installed in systems such as the supercomputer Fugaku,
> > FX700, and FX1000, but since the A64FX functions have not yet been
> > implemented in QEMU, we would like to be able to develop programs in QEMU
> > to use the HPC extensions.
> >
> > Currently, the register specifications for the HPC extensions have been
> > published in [2],  so we would like to implement these registers in QEMU and
> > make them accessible.
> > Eventually, we would also like to consider a mechanism that allows HPC
> > extensions  to operate within the scope of the published information.
> >
> > We would like your comments on the following points in this RFC.
> >
> > 1) Is target/arm/helper.c enough to implement the register (ARMCPRegInfo
> > structure) of HPC extension function of A64FX?
> >
> > 2) Is it OK to specify the option to set the HPC extension of A64FX as 
> > follows,
> > for example?
> >
> > -M virt -cpu max,a64fx-hpc-sec=on (*sector cache function) -M virt -cpu
> > max,a64fx-hpc-hwpf=on (*hardware prefetvh assist function) -M virt -cpu
> > max,a64fx-hpc-hwb=on (*hardware barrier function)
> >
> > It is also possible to implement something like -cpu a64fx, but since we 
> > don't
> > know if we can implement it immediately, we assume that we will use the -cpu
> > max option first.
> >
> > Since there is no example of A64FX function implemented in QEMU, we would
> > appreciate your comments before we post a patch.
> >
> > Best regards.