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[PATCH 11/13] target/arm: Provide ARMv8.4-PMU in '-cpu max'
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From: |
Peter Maydell |
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Subject: |
[PATCH 11/13] target/arm: Provide ARMv8.4-PMU in '-cpu max' |
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Date: |
Tue, 11 Feb 2020 17:37:24 +0000 |
Set the ID register bits to provide ARMv8.4-PMU (and implicitly
also ARMv8.1-PMU) in the 'max' CPU.
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu64.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 4b4b134ef84..5b8b7a9d4b8 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -693,6 +693,14 @@ static void aarch64_max_initfn(Object *obj)
u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
cpu->isar.id_isar6 = u;
+ u = cpu->isar.id_aa64dfr0;
+ u = FIELD_DP32(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
+ cpu->isar.id_aa64dfr0 = u;
+
+ u = cpu->isar.id_dfr0;
+ u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+ cpu->isar.id_dfr0 = u;
+
/*
* FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
* so do not set MVFR1.FPHP. Strictly speaking this is not legal,
--
2.20.1
- Re: [PATCH 06/13] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field, (continued)
- [PATCH 09/13] target/arm: Implement ARMv8.1-PMU extension, Peter Maydell, 2020/02/11
- [PATCH 05/13] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1, Peter Maydell, 2020/02/11
- [PATCH 01/13] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers, Peter Maydell, 2020/02/11
- [PATCH 11/13] target/arm: Provide ARMv8.4-PMU in '-cpu max',
Peter Maydell <=
- [PATCH 08/13] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks, Peter Maydell, 2020/02/11
- [PATCH 04/13] target/arm: Factor out PMU register definitions, Peter Maydell, 2020/02/11
- [PATCH 07/13] target/arm: Define an aa32_pmu_8_1 isar feature test function, Peter Maydell, 2020/02/11
- [PATCH 13/13] target/arm: Correct handling of PMCR_EL0.LC bit, Peter Maydell, 2020/02/11