On Sun, 2008-05-18 at 23:46 -0700, Garrett Cooper wrote:
This is a 2 part problem:
Part 1 (understanding the documentation):
I'm writing canned sequences in a series of makefiles and I'm
confused.. In http://www.gnu.org/software/make/manual/make.html#Sequences
the documentation claims:
"The define directive does not expand variable references and
function calls in the canned sequence; the `$' characters,
parentheses, variable names, and so on, all become part of the value
of the variable you are defining."
However, in
http://www.gnu.org/software/make/manual/make.html#Call-Function
the documentation claims:
"Note that variable is the name of a variable; not a reference to
that variable. Therefore you would not normally use a `$' or
parentheses when writing it. (You can, however, use a variable
reference in the name if you want the name not to be a constant.)"
The example in
http://www.gnu.org/software/make/manual/make.html#Eval-Function
also uses $$ instead of $ when referencing variables.
Yes. I guess it would be helpful if you'd point out exactly what it
is
you don't understand. I don't see any issue with these two
statements:
they are talking about completely different things. The first
statement
talks about the value of a variable defined with define/endef. The
second statement is talking about the NAME of the variable to be
expanded by the call function; as in: $(call
NAME,value1,value2,value3)
They don't have anything to do with each other that I can see, so I'm
not sure why you're comparing/contrasting them.
Part 2 (trying to apply my understanding):
So, my point of confusion comes in when I'm trying to determine when
to use $$ or $, in particular with recursive $(eval $(call ))
statements.
A (simple) working example is provided as "simple_makefile.mk". A
more complex example (master_rules.mk) doesn't work however (nothing
that depends on these rules builds / cleans like it should -- EXCEPT
when I define the dependent variables outside of the define!)...
You're going to have to make this simpler if you want help with it. A
good debugging technique is to replace eval with a function like
warn or
info that expands its argument (like eval does) then prints it. The
output you see by doing this is the text that eval will evaluate. So,
hopefully this will let you see what might be wrong with your makefile
fragments.
Second, note that this construct:
$(eval $(call FOO))
with no arguments to the call function, is useless. It's EXACTLY the
same behavior as:
$(eval $(FOO))
Third, having eval nested inside call inside eval like you're doing is
really asking to have your mind blown. You might consider whether you
can leverage other methods for simplifying your makefile: pattern
rules,
static pattern rules, target-specific variables, or something. I'm
not
sure exactly what your goal is so it's hard to recommend something.