Confusion over documentation wording, variable usage, and scope

[Garrett Cooper]

This is a 2 part problem:

Part 1 (understanding the documentation):

	I'm writing canned sequences in a series of makefiles and I'm  
confused.. In http://www.gnu.org/software/make/manual/make.html#Sequences 
 the documentation claims:

	"The define directive does not expand variable references and  
function calls in the canned sequence; the `$' characters,  
parentheses, variable names, and so on, all become part of the value  
of the variable you are defining."

	However, in http://www.gnu.org/software/make/manual/make.html#Call-Function 
 the documentation claims:

	"Note that variable is the name of a variable; not a reference to  
that variable. Therefore you would not normally use a `$' or  
parentheses when writing it. (You can, however, use a variable  
reference in the name if you want the name not to be a constant.)"

	The example in http://www.gnu.org/software/make/manual/make.html#Eval-Function 
 also uses $$ instead of $ when referencing variables.

Part 2 (trying to apply my understanding):

	So, my point of confusion comes in when I'm trying to determine when  
to use $$ or $, in particular with recursive $(eval $(call ))  
statements.

	A (simple) working example is provided as "simple_makefile.mk". A  
more complex example (master_rules.mk) doesn't work however (nothing  
that depends on these rules builds / cleans like it should -- EXCEPT  
when I define the dependent variables outside of the define!)...

        Any help or recommendations are more than welcome.

	Reading Makefile and config.mk aren't necessary, but they're here  
just as a reference for what I'm trying to do.

Thanks,
-Garrett

master_rules.mk
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Makefile
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simple_makefile.mk
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config.mk
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