Re: Fwd: memory probing

[Douglas Wade Needham]

First the northbridge/southbridge.  Here is a pic..


                                    +--------+  +----------+
                                    |  CPU   |--| L2 CACHE |
                                    +--------+  +----------+
                                        |
                                        |  CPU Bus
                                        |
                                 +-------------+    +-----+
                                 | Northbridge |----| RAM |
                                 +-------------+    +-----+
                                        |
                                        | Local Bus (typ. PCI)
                                        |
                                 +-------------+
                                 | Southbridge |
                                 +-------------+
                                        |
                                        |
                                        | Periph Bus (PCI, ISA.)
                                        |

The northbridge is primarily responsible for memory control, as well
as providing a common bus for other controllers and bridge chips.
Most of the time, this is a PCI bus.  The southbridge, OTOH is the one
which is more versatile, typically acting as a bridge between the
intermediate bus and other busses used for peripherals (ISA, PCI,
etc.).  Since fewer chips is often a major design goal, the
southbridge also tends to include things like an IDE controller,
floppy controller, COM ports, etc.  In some cases, the north and south
bridges may be combined into a single chip.  In other cases (such as
on the MCP-750), the northbridge is actually split in two, and the
local bus functionallity is separated from the memory controller
function, and both talk directly to the CPU.

As for details on your bridge chips, you will probably need to do a
NDA with some vendor to get the spec sheets which tell you the
details.  The chip which has responsibility for the memory, which is
generally your northbridge (such as a Intel 440BX), will during
initialization do reads of special info on your memory modules using
I2C cycles.  As a result, this chip can determine parameters such as
RAM speed, size, etc.  Some bridge chips will do this as a result of a
reset, while others may require a command to be issued to do this.
Now from what I have seen, more will do it automatically when the reset
signal is asserted, instead of requiring for a command to be issued.

BTW...reading this sort of information is generally done by the boot
firmware (e.g. "BIOS"), as it is often needed so that it knows where
the bootstrap can be loaded.  It is also sometimes the case that the
bootstrap will not read this information itself, but will instead
either be passed the info, or will load the main program (kernel,
etc.) based upon a set of assumptions.

- Doug

Quoting alfred hitch (address@hidden):
> Hi Stefan,
> 
> thanks for your reply, 
> but I am still not very clear on how this is done by say bios on x86
> plattforms, ?
> can u please expain in more detail abt this north bridge , south
> bridge thing .. ?
> 
> I would like to try and recreate the same way of probing for our set
> up, may be its not that portable , but atleast works on our series of
> products ..
> 
> What registers are these ? 
> 
> Cheers,
> Alfred
> 
> On 5/10/05, Stefan Reinauer <address@hidden> wrote:
> > * alfred hitch <address@hidden> [050510 12:23]:
> > > anyways, how can u get this from processor also ?
> > 
> > The processor has little to nothing to do with this.. it's dependent on
> > the northbridge and southbridge.
> > 
> > > I vaguely remember see'ing some code where someone on a i386 based
> > > plattform but WITHOUT bios, used smbus protocol to talk to a device
> > > across PIIX4 to get the info.
> > 
> > Which might work on one motherboard and fail on another. Even if they
> > both have a PIIX4.
> > 
> > > I am not familiar with PC architecture, so can someone tell me if
> > > there is some standard chip  (memory controller? ?) where one can read
> > > this on PC type arch. atleast ?
> > 
> > No. Not in a portable way. That's why BIOS provides the e820 table.
> > 
> > > I am on  a IXDP425 plattform, and so far I cannot see any such
> > > register on the data sheets ..
> > 
> > They are usually not disclosed in publically available datasheets.
> > 
> >   Stefan
> > 
> > 
> > _______________________________________________
> > Grub-devel mailing list
> > address@hidden
> > http://lists.gnu.org/mailman/listinfo/grub-devel
> >
> 
> 
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> address@hidden
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-- 
Douglas Wade Needham - KA8ZRT        UN*X Consultant & UW/BSD kernel programmer
Email:  cinnion @ ka8zrt . com       http://cinnion.ka8zrt.com
Disclaimer: My opinions are my own.  Since I don't want them, why
            should my employer, or anybody else for that matter!