Re: Segmentation Violation at sillicon compiler placement

[Naohiko Shimizu]

Thank you Dr. Rubin,

It works fine with the option setting.

I will use Electric for my class in stead of Magic in the
next semester.

For EDIF generation with Icarus Verilog, I am in the half way. 
Then I will try as soon as possible.

I also want to import Alliance's scalable standard cell library
to Electric for the EDIF. I am now working on MOSIS compatible
design rule definition for Alliance.
Perhaps I will need more study on Electric and help for these works.

Regards,
Naohiko Shimizu

http://shimizu-lab.dt.u-tokai.ac.jp/