Re: Segmentation Violation at sillicon compiler placement

[Steven Rubin]

> I have a trouble when making a simple example for place and route
> with following steps.
>
> 1. make a new facet with schematic. Change technology as schematic-digital.
> 2. make a logic as
>
>    in1 --
>             and  (negate) -- buffer (negate) -- out
>    in2 --
>
> 3. change technology as mocmos
> 4. sillicon compiler 1) read mosis library, 2) get network
> 5. sillicon compiler place --> will cause segmentation violation!
>
> I tried with electric-6.0.8 and 6.0.5 and both crashed with segv.
> I suceeded with
>
>  in -- buffer (negate) --buffer(negate) --out
>
> and
>
>   in1 ---------------------  and (negate) --- out
>   in2 --- buffer(negate) --
>
> circuits without trouble.
>
> Do you have any idea or workaround?
>
> BTW, I want to make Icarus Verilog to generate valid EDIF file.
> I hope I can use Electric to generate layout with the EDIF file.

One of the sensitivities that the Silicon Compiler has is that you have to 
set the number of rows of circuitry in advance.  I believe the default is 4 
rows.  However, if you have a circuit so simple that there aren't even 4 
components, then the system crashes.  Go into the "Silicon Compiler 
Options" and set it to 1 row.

As far as EDIF goes, Electric can read EDIF schematics.  From the 
schematics, you can convert to VHDL, and from there to a netlist for the 
Silicon Compiler.

   -Steven Rubin