on simulations and bugs

[Tuukka Toivonen]

The component panel has 4 flipflops and NONE of them work! Quite
horrible. JK almost works: when I set J, the output goes 1 at the next
clock edge. However, when I set K, the output goes 0 immediately and not
at the next edge as it should.

What comes to D-flipflop, I fixed the bug, patch follows at the end.

> >         "ERROR: Model 'MUX2' not found, simulation aborted"
> The simulator doesn't have models for all of the analog schematic symbols.
I suppose this is same for digital components since MUX is one of those. 
However, it seems that I found a way to enable muxes: I just wrote
netlist-als for MUX1 and MUX2 and it seems to work, more or less!
-----
model MUX1(a1,sel,z)
g1: mux1fun(a1,sel,z)

gate mux1fun(a,sel,z)
t: delta=0
i: sel=H a=L o: z=L
i: sel=H a=H o: z=H
i: sel=L o: address@hidden
i: o: z=X
load: sel=1.0 a=1.0
-----
MUX requires that "sel" is a bus, so I'll create a completely custom
component for this later. Meanwhile, couple of questions:
There are two possibilities: either my xmit gate is perfect and should be
included with Electric, or more likely there are problems with it. I know
loads, fanouts and delays are just wrong, but logically is it sane?
Could this be made better?

> >First I thought that the third pin in a buffer/inverter would do that but
> them.  Thus, a terminal may be understood and used by an output deck 
> generator, but not by some other simulation interface.  The built-in 
Would it be difficult to change Electric so that it uses "inverter3" or
something when the third pin is connected, just like it does for and2,
and3, and so on? Then I could just write netlist-als model for it.

> You have indeed uncovered a bug.  The conversion of busses to VHDL is 
> flawed.  I will look into it.
This is definitely the biggest problem with Electric right now, for me.

You mentioned IRSIM. I found it and it looked very promising: a version of
it can do power calculations, and that is what I need. Unfortunately
generated IRSIM deck is empty for digital schematics. Is there any way
to convert digital schematics for IRSIM? Any third-party programs?

Alternatively, is there any similar simulator for which Electric can
generate a digital deck?

Patch here:

--- electric-6.03/src/vhdl/vhdl.c.orig  Tue Jun  5 21:46:20 2001
+++ electric-6.03/src/vhdl/vhdl.c       Tue Jun  5 21:46:51 2001
@@ -1657,13 +1657,13 @@
                                        *special = BLOCKFLOP;
                                        break;
                                case FFTYPED:
-                                       (void)strcpy(pt, "dsff");
+                                       (void)strcpy(pt, "deff");
                                        *special = BLOCKFLOPDS;
                                        for(pi = ni->firstportarcinst; pi != 
NOPORTARCINST; pi = pi->nextportarcinst)
                                        {
                                                if 
(namesame(pi->proto->protoname, "clear") == 0)
                                                {
-                                                       (void)strcpy(pt, 
"drff");
+                                                       (void)strcpy(pt, 
"deff");
                                                        *special = BLOCKFLOPDR;
                                                        break;
                                                }
--- electric-6.03/src/vhdl/vhdlals.c.orig       Tue Jun  5 21:47:15 2001
+++ electric-6.03/src/vhdl/vhdlals.c    Tue Jun  5 21:47:56 2001
@@ -172,7 +172,7 @@
        };
        static char *DFF[] =
        {
-               "model dsff(d, clk, pr, q)",
+               "model deff(d, clk, pr, q)",
                "n: DFFLOP(d, clk, q)",
                "function DFFLOP(d, clk, q)",
                "i: d, clk",
@@ -310,7 +310,7 @@
                        vhdl_dumpfunction(gate, JKFF);
                        ulist->numref = 0;
                        total--;
-               } else if (strcmp(gate, "dsff") == 0)
+               } else if (strcmp(gate, "deff") == 0)
                {
                        vhdl_dumpfunction(gate, DFF);
                        ulist->numref = 0;