RE: [avr-libc-dev] Re: [bug #25300] Additional i/o port names

[Weddington, Eric]

> -----Original Message-----
> From: 
> address@hidden 
> [mailto:address@hidden
> org] On Behalf Of Frédéric Nadeau
> Sent: Friday, April 10, 2009 1:31 PM
> To: address@hidden
> Subject: Re: [avr-libc-dev] Re: [bug #25300] Additional i/o port names
> 
> Hi there,
> 
> I'm working on the duplicate thing and I'm facing a critical issue. It
> has been decided that we should not care mutch if pins where active
> low or active high(such as SS, RD, WR, etc).
> 
> http://www.atmel.com/dyn/resources/prod_documents/doc1477.pdf
> See page 2 PB0 and PB1
> 
> This seems to be as a legitimate duplicate. This will end up in the
> following as a duplicate entry in the pin define section:
> #define OC1A_DDR DDRB
> 
> Any opinion for a work around, better idea?

*sigh*

Unfortunately, I don't have a better idea. It looks like that we will have to 
take into account inverted signals in the naming scheme. (As a side note, I 
really wish the XML files were more consistent. It looks like the ATtiny26.xml 
file has yet another way to do the pin mappings.)

I'm open to ideas on a naming scheme.