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[PATCH for-8.1 v2 17/26] target/riscv: write env->misa_ext* in register_
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH for-8.1 v2 17/26] target/riscv: write env->misa_ext* in register_generic_cpu_props() |
Date: |
Tue, 14 Mar 2023 13:49:39 -0300 |
In the process of creating the user-facing flags in
register_generic_cpu_props() we're also setting default values for the
cpu->cfg flags that represents MISA bits.
Leaving it as is will cause a discrepancy between users of this function
(at this moment the non-named CPUs) and named CPUs. Named CPUs are using
set_misa() with a non-zero 'ext' value, writing cpu->cfg in the process.
They'll reach riscv_cpu_realize() in a state where env->misa_ext will
reflect cpu->cfg, allowing functions to choose whether to use
env->misa_ext or cpu->cfg to validate MISA bits.
If we guarantee that env->misa_ext will always reflect cpu->cfg at the
start of riscv_cpu_realize(), functions will be able to no longer rely
on cpu->cfg for MISA validation. This happens to be one blocker we have to
properly support write_misa().
Sync env->misa_ext* in register_generic_cpu_props(). This will leave
only a single place where there's a cpu->cfg change that needs to be
converted back to env->misa_ext*: right after disabling priv spec
extensions, at the end of riscv_cpu_validate_set_extensions(). We'll
deal with it shortly.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 133807e39f..af5a1e6a43 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1595,10 +1595,12 @@ static Property riscv_cpu_extensions[] = {
* Register generic CPU props with user-facing flags declared
* in riscv_cpu_extensions[].
*
- * Note that this will overwrite existing values in cpu->cfg.
+ * Note that this will overwrite existing values in cpu->cfg
+ * and MISA.
*/
static void register_generic_cpu_props(Object *obj)
{
+ RISCVCPU *cpu = RISCV_CPU(obj);
Property *prop;
DeviceState *dev = DEVICE(obj);
@@ -1609,6 +1611,10 @@ static void register_generic_cpu_props(Object *obj)
#ifndef CONFIG_USER_ONLY
riscv_add_satp_mode_properties(obj);
#endif
+
+ /* Keep env->misa_ext and misa_ext_mask updated */
+ cpu->env.misa_ext = riscv_get_misa_ext_with_cpucfg(&cpu->cfg);
+ cpu->env.misa_ext_mask = cpu->env.misa_ext;
}
static Property riscv_cpu_properties[] = {
--
2.39.2
- [PATCH for-8.1 v2 10/26] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions(), (continued)
- [PATCH for-8.1 v2 10/26] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 11/26] target/riscv/cpu.c: set cpu config in set_misa(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 12/26] target/riscv/cpu.c: redesign register_cpu_props(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 13/26] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers, Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 14/26] target/riscv: add RVG, Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 15/26] target/riscv: do not allow RVG in write_misa(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 16/26] target/riscv/cpu.c: split RVG code from validate_set_extensions(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 17/26] target/riscv: write env->misa_ext* in register_generic_cpu_props(),
Daniel Henrique Barboza <=
- [PATCH for-8.1 v2 18/26] target/risc/cpu.c: add riscv_cpu_validate_misa_ext(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 19/26] target/riscv/cpu:c add misa_ext V-> D & F dependency, Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 20/26] target/riscv: move riscv_cpu_validate_v() to validate_misa_ext(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 21/26] target/riscv: validate_misa_ext() now validates a misa_ext val, Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 25/26] target/riscv: rework write_misa(), Daniel Henrique Barboza, 2023/03/14