[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH for-8.1 v2 15/26] target/riscv: do not allow RVG in write_misa()
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH for-8.1 v2 15/26] target/riscv: do not allow RVG in write_misa() |
Date: |
Tue, 14 Mar 2023 13:49:37 -0300 |
We're getting ready to use riscv_cpu_validate_set_extensions() to unify
the handling of write_misa() with the rest of the code base. But first
we need to deal with RVG.
The 'G' virtual extension enables a set of extensions in the CPU. At
this moment, this is done at the start of our validation step in
riscv_cpu_validate_set_extensions(). This means that enabling G will
enable other extensions in the CPU before resuming the validation.
This also means that, in case a write_misa() validation fails, we're
going to set cpu->cfg attributes that are unrelated to misa_ext bits
(icsr and ifencei). These would be 2 extra states that we would need to
store to fallback from a validation failure.
Since write_misa() is still on experimental state let's make our lives
easier for now and disable RVG updates.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/csr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d522efc0b6..918d442ebd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1348,6 +1348,11 @@ static RISCVException write_misa(CPURISCVState *env, int
csrno,
return RISCV_EXCP_NONE;
}
+ /* Changing 'G' state is unsupported */
+ if (val & RVG) {
+ return RISCV_EXCP_NONE;
+ }
+
/* 'I' or 'E' must be present */
if (!(val & (RVI | RVE))) {
/* It is not, drop write to misa */
--
2.39.2
- [PATCH for-8.1 v2 05/26] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers, (continued)
- [PATCH for-8.1 v2 05/26] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers, Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 06/26] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 07/26] target/riscv: move pmp and epmp validations to validate_set_extensions(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 08/26] target/riscv/cpu.c: validate extensions before riscv_timer_init(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 09/26] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 10/26] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 11/26] target/riscv/cpu.c: set cpu config in set_misa(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 12/26] target/riscv/cpu.c: redesign register_cpu_props(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 13/26] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers, Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 14/26] target/riscv: add RVG, Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 15/26] target/riscv: do not allow RVG in write_misa(),
Daniel Henrique Barboza <=
- [PATCH for-8.1 v2 16/26] target/riscv/cpu.c: split RVG code from validate_set_extensions(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 17/26] target/riscv: write env->misa_ext* in register_generic_cpu_props(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 18/26] target/risc/cpu.c: add riscv_cpu_validate_misa_ext(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 19/26] target/riscv/cpu:c add misa_ext V-> D & F dependency, Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 20/26] target/riscv: move riscv_cpu_validate_v() to validate_misa_ext(), Daniel Henrique Barboza, 2023/03/14
- [PATCH for-8.1 v2 21/26] target/riscv: validate_misa_ext() now validates a misa_ext val, Daniel Henrique Barboza, 2023/03/14