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[PULL 14/22] riscv: Correctly set the device-tree entry 'mmu-type'
From: |
Palmer Dabbelt |
Subject: |
[PULL 14/22] riscv: Correctly set the device-tree entry 'mmu-type' |
Date: |
Mon, 6 Mar 2023 14:02:51 -0800 |
From: Alexandre Ghiti <alexghiti@rivosinc.com>
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20230303131252.892893-6-alexghiti@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
hw/riscv/virt.c | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 7f70fa11a1..26eb81d036 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -228,8 +228,9 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
int cpu;
uint32_t cpu_phandle;
MachineState *ms = MACHINE(s);
- char *name, *cpu_name, *core_name, *intc_name;
+ char *name, *cpu_name, *core_name, *intc_name, *sv_name;
bool is_32_bit = riscv_is_32bit(&s->soc[0]);
+ uint8_t satp_mode_max;
for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu];
@@ -239,13 +240,15 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
cpu_name = g_strdup_printf("/cpus/cpu@%d",
s->soc[socket].hartid_base + cpu);
qemu_fdt_add_subnode(ms->fdt, cpu_name);
- if (cpu_ptr->cfg.mmu) {
- qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
- (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
- } else {
- qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
- "riscv,none");
- }
+
+ satp_mode_max = satp_mode_max_from_map(
+ s->soc[socket].harts[cpu].cfg.satp_mode.map);
+ sv_name = g_strdup_printf("riscv,%s",
+ satp_mode_str(satp_mode_max, is_32_bit));
+ qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name);
+ g_free(sv_name);
+
+
name = riscv_isa_string(cpu_ptr);
qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
g_free(name);
--
2.39.2
- [PULL 02/22] target/riscv: implement Zicbom extension, (continued)
- [PULL 02/22] target/riscv: implement Zicbom extension, Palmer Dabbelt, 2023/03/06
- [PULL 05/22] disas/riscv Fix ctzw disassemble, Palmer Dabbelt, 2023/03/06
- [PULL 03/22] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder, Palmer Dabbelt, 2023/03/06
- [PULL 04/22] hw/riscv/virt.c: add cbo[mz]-block-size fdt properties, Palmer Dabbelt, 2023/03/06
- [PULL 06/22] target/riscv: cpu: Implement get_arch_id callback, Palmer Dabbelt, 2023/03/06
- [PULL 08/22] gitlab/opensbi: Move to docker:stable, Palmer Dabbelt, 2023/03/06
- [PULL 07/22] hw: intc: Use cpu_by_arch_id to fetch CPU state, Palmer Dabbelt, 2023/03/06
- [PULL 11/22] riscv: Change type of valid_vm_1_10_[32|64] to bool, Palmer Dabbelt, 2023/03/06
- [PULL 10/22] riscv: Pass Object to register_cpu_props instead of DeviceState, Palmer Dabbelt, 2023/03/06
- [PULL 12/22] riscv: Allow user to set the satp mode, Palmer Dabbelt, 2023/03/06
- [PULL 14/22] riscv: Correctly set the device-tree entry 'mmu-type',
Palmer Dabbelt <=
- [PULL 13/22] riscv: Introduce satp mode hw capabilities, Palmer Dabbelt, 2023/03/06
- [PULL 09/22] roms/opensbi: Upgrade from v1.1 to v1.2, Palmer Dabbelt, 2023/03/06
- [PULL 17/22] hw/riscv/virt: Add memmap pointer to RiscVVirtState, Palmer Dabbelt, 2023/03/06
- [PULL 15/22] hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields, Palmer Dabbelt, 2023/03/06
- [PULL 16/22] hw/riscv/virt: Add a switch to disable ACPI, Palmer Dabbelt, 2023/03/06
- [PULL 19/22] hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT, Palmer Dabbelt, 2023/03/06
- [PULL 18/22] hw/riscv/virt: Enable basic ACPI infrastructure, Palmer Dabbelt, 2023/03/06
- [PULL 22/22] MAINTAINERS: Add entry for RISC-V ACPI, Palmer Dabbelt, 2023/03/06
- [PULL 21/22] hw/riscv/virt.c: Initialize the ACPI tables, Palmer Dabbelt, 2023/03/06
- [PULL 20/22] hw/riscv/virt: virt-acpi-build.c: Add RHCT Table, Palmer Dabbelt, 2023/03/06