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[PATCH v11 5/5] riscv: Correctly set the device-tree entry 'mmu-type'
From: |
Alexandre Ghiti |
Subject: |
[PATCH v11 5/5] riscv: Correctly set the device-tree entry 'mmu-type' |
Date: |
Fri, 3 Mar 2023 14:12:52 +0100 |
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
hw/riscv/virt.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 86c4adc0c9..59922d6965 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -228,8 +228,9 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
int cpu;
uint32_t cpu_phandle;
MachineState *ms = MACHINE(s);
- char *name, *cpu_name, *core_name, *intc_name;
+ char *name, *cpu_name, *core_name, *intc_name, *sv_name;
bool is_32_bit = riscv_is_32bit(&s->soc[0]);
+ uint8_t satp_mode_max;
for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
cpu_phandle = (*phandle)++;
@@ -237,14 +238,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
cpu_name = g_strdup_printf("/cpus/cpu@%d",
s->soc[socket].hartid_base + cpu);
qemu_fdt_add_subnode(ms->fdt, cpu_name);
- if (riscv_feature(&s->soc[socket].harts[cpu].env,
- RISCV_FEATURE_MMU)) {
- qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
- (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
- } else {
- qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
- "riscv,none");
- }
+
+ satp_mode_max = satp_mode_max_from_map(
+ s->soc[socket].harts[cpu].cfg.satp_mode.map);
+ sv_name = g_strdup_printf("riscv,%s",
+ satp_mode_str(satp_mode_max, is_32_bit));
+ qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name);
+ g_free(sv_name);
+
name = riscv_isa_string(&s->soc[socket].harts[cpu]);
qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
g_free(name);
--
2.37.2
- [PATCH v11 0/5] riscv: Allow user to set the satp mode, Alexandre Ghiti, 2023/03/03
- [PATCH v11 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState, Alexandre Ghiti, 2023/03/03
- [PATCH v11 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool, Alexandre Ghiti, 2023/03/03
- [PATCH v11 3/5] riscv: Allow user to set the satp mode, Alexandre Ghiti, 2023/03/03
- [PATCH v11 4/5] riscv: Introduce satp mode hw capabilities, Alexandre Ghiti, 2023/03/03
- [PATCH v11 5/5] riscv: Correctly set the device-tree entry 'mmu-type',
Alexandre Ghiti <=
- Re: [PATCH v11 0/5] riscv: Allow user to set the satp mode, Palmer Dabbelt, 2023/03/05