[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 03/22] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder
From: |
Palmer Dabbelt |
Subject: |
[PULL 03/22] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder |
Date: |
Mon, 6 Mar 2023 14:02:40 -0800 |
From: Christoph Muellner <cmuellner@linux.com>
The cmo.prefetch instructions are nops for QEMU (no emulation of the
memory hierarchy, no illegal instructions, no permission faults, no
traps).
Add a comment noting where they would be decoded in case cbo.prefetch
instructions become relevant in the future.
Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Christoph Muellner <cmuellner@linux.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230224132536.552293-5-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/insn32.decode | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 282e41aa3e..73d5d1b045 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -134,6 +134,7 @@ addi ............ ..... 000 ..... 0010011 @i
slti ............ ..... 010 ..... 0010011 @i
sltiu ............ ..... 011 ..... 0010011 @i
xori ............ ..... 100 ..... 0010011 @i
+# cbo.prefetch_{i,r,m} instructions are ori with rd=x0 and not decoded.
ori ............ ..... 110 ..... 0010011 @i
andi ............ ..... 111 ..... 0010011 @i
slli 00000. ...... ..... 001 ..... 0010011 @sh
--
2.39.2
- [PULL 00/22] Sixth RISC-V PR for 8.0, Palmer Dabbelt, 2023/03/06
- [PULL 01/22] target/riscv: implement Zicboz extension, Palmer Dabbelt, 2023/03/06
- [PULL 02/22] target/riscv: implement Zicbom extension, Palmer Dabbelt, 2023/03/06
- [PULL 05/22] disas/riscv Fix ctzw disassemble, Palmer Dabbelt, 2023/03/06
- [PULL 03/22] target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder,
Palmer Dabbelt <=
- [PULL 04/22] hw/riscv/virt.c: add cbo[mz]-block-size fdt properties, Palmer Dabbelt, 2023/03/06
- [PULL 06/22] target/riscv: cpu: Implement get_arch_id callback, Palmer Dabbelt, 2023/03/06
- [PULL 08/22] gitlab/opensbi: Move to docker:stable, Palmer Dabbelt, 2023/03/06
- [PULL 07/22] hw: intc: Use cpu_by_arch_id to fetch CPU state, Palmer Dabbelt, 2023/03/06
- [PULL 11/22] riscv: Change type of valid_vm_1_10_[32|64] to bool, Palmer Dabbelt, 2023/03/06
- [PULL 10/22] riscv: Pass Object to register_cpu_props instead of DeviceState, Palmer Dabbelt, 2023/03/06
- [PULL 12/22] riscv: Allow user to set the satp mode, Palmer Dabbelt, 2023/03/06
- [PULL 14/22] riscv: Correctly set the device-tree entry 'mmu-type', Palmer Dabbelt, 2023/03/06
- [PULL 13/22] riscv: Introduce satp mode hw capabilities, Palmer Dabbelt, 2023/03/06
- [PULL 09/22] roms/opensbi: Upgrade from v1.1 to v1.2, Palmer Dabbelt, 2023/03/06