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Re: [PATCH v2 1/5] target/riscv: Fix coding style on "G" expansion
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v2 1/5] target/riscv: Fix coding style on "G" expansion |
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Date: |
Tue, 17 May 2022 10:38:02 +1000 |
On Sun, May 15, 2022 at 12:56 PM Tsukasa OI
<research_trasio@irq.a4lg.com> wrote:
>
> Because ext_? members are boolean variables, operator `&&' should be
> used instead of `&'.
>
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ccacdee215..00bf26ec8b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -596,8 +596,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> return;
> }
>
> - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
> - cpu->cfg.ext_a & cpu->cfg.ext_f &
> + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
> + cpu->cfg.ext_a && cpu->cfg.ext_f &&
> cpu->cfg.ext_d)) {
> warn_report("Setting G will also set IMAFD");
> cpu->cfg.ext_i = true;
> --
> 2.34.1
>
- [PATCH 1/5] target/riscv: Fix "G" extension expansion typing, (continued)
- [PATCH 1/5] target/riscv: Fix "G" extension expansion typing, Tsukasa OI, 2022/05/13
- [PATCH 2/5] target/riscv: Disable "G" by default, Tsukasa OI, 2022/05/13
- [PATCH 3/5] target/riscv: Change "G" expansion, Tsukasa OI, 2022/05/13
- [PATCH 4/5] target/riscv: FP extension requirements, Tsukasa OI, 2022/05/13
- [PATCH 5/5] target/riscv: Move/refactor ISA extension checks, Tsukasa OI, 2022/05/13
- [PATCH v2 0/5] target/riscv: Enhanced ISA extension checks, Tsukasa OI, 2022/05/14
- [PATCH v2 3/5] target/riscv: Change "G" expansion, Tsukasa OI, 2022/05/14
- [PATCH v2 4/5] target/riscv: FP extension requirements, Tsukasa OI, 2022/05/14