Re: [PATCH v2 3/5] target/riscv: Change "G" expansion

[Alistair Francis]

On Sun, May 15, 2022 at 12:56 PM Tsukasa OI
<research_trasio@irq.a4lg.com> wrote:
>
> On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei".
> Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to
> be (virtually) enabled as well, it should be safe to change its expansion.
>
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3ea68d5cd7..0854ca9103 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -598,13 +598,16 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>
>          if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
>                                  cpu->cfg.ext_a && cpu->cfg.ext_f &&
> -                                cpu->cfg.ext_d)) {
> -            warn_report("Setting G will also set IMAFD");
> +                                cpu->cfg.ext_d &&
> +                                cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
> +            warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
>              cpu->cfg.ext_i = true;
>              cpu->cfg.ext_m = true;
>              cpu->cfg.ext_a = true;
>              cpu->cfg.ext_f = true;
>              cpu->cfg.ext_d = true;
> +            cpu->cfg.ext_icsr = true;
> +            cpu->cfg.ext_ifencei = true;
>          }
>
>          if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
> --
> 2.34.1
>