Re: [PATCH v2 2/2] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)

[Alistair Francis]

On Sat, May 14, 2022 at 4:30 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> If specified CPU configuration is not valid, not just it prints error
> message, it aborts and generates core dumps (depends on the operating
> system).  This kind of error handling should be used only when a serious
> runtime error occurs.
>
> This commit makes error handling on CPU configuration more generous on
> sifive_e/u and opentitan machines.  It now just prints error message and
> quits (without coredumps and aborts).
>
> This is separate from spike/virt because it involves different type
> (TYPE_RISCV_HART_ARRAY) on sifive_e/u and opentitan machines.
>
> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/opentitan.c | 2 +-
>  hw/riscv/sifive_e.c  | 2 +-
>  hw/riscv/sifive_u.c  | 4 ++--
>  3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 2d401dcb23..4495a2c039 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -142,7 +142,7 @@ static void lowrisc_ibex_soc_realize(DeviceState 
> *dev_soc, Error **errp)
>      object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
>                              &error_abort);
>      object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, 
> &error_abort);
> -    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
> +    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
>
>      /* Boot ROM */
>      memory_region_init_rom(&s->rom, OBJECT(dev_soc), 
> "riscv.lowrisc.ibex.rom",
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index dcb87b6cfd..d65d2fd869 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -195,7 +195,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error 
> **errp)
>
>      object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
>                              &error_abort);
> -    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
> +    sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
>
>      /* Mask ROM */
>      memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index cc8c7637cb..a2495b5ae7 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -830,8 +830,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error 
> **errp)
>      qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
>      qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
>
> -    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
> -    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
> +    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal);
> +    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal);
>      /*
>       * The cluster must be realized after the RISC-V hart array container,
>       * as the container's CPU object is only created on realize, and the
> --
> 2.34.1
>