[PATCH 0/2] hw/riscv: Make CPU config error handling generous

[Tsukasa OI]

Hello,

This patchset involves error handling on RISC-V CPU configuration error.

For instance:

    -cpu rv64,f=on,zfinx=on

This is an example of invalid CPU configuration because "F" and "Zfinx"
cannot coexist.  Detecting such error is a good thing.

The bad thing is, it aborts when such invalid configuration is detected.
I'm making changes to QEMU on Ubuntu 22.04 LTS but once I got a pop-up
window asking whether to send a crash report.  Even if not, it generates
core dumps.  That's not what I wanted.

    Example of error message before this patchset:
    Unexpected error in riscv_cpu_realize() at 
../../../../src/qemu/target/riscv/cpu.c:718:
    qemu-system-riscv64: 'Zfinx' cannot be supported together with 'F', 'D', 
'Zfh', 'Zfhmin'
    Aborted (core dumped)
    $ (returns to shell but may show error report window on some OS)

Such extreme error handling should be only used on serious runtime errors,
not for minor user-configuration mistakes (that can be easily and *safely*
detectable).

    Example of error message after this patchset:
    qemu-system-riscv64: 'Zfinx' cannot be supported together with 'F', 'D', 
'Zfh', 'Zfhmin'
    $ (returns to shell with error status [$?] of 1)

This patchset resolves this problem on following machines, changing error
handling structure from `error_abort' (aborts and generates core dumps
[depends on OS] on error) to `error_fatal' (shows error message and quits
with error status 1 on error):

-   spike (QEMU default)
-   virt
-   sifive_e
-   sifive_u
-   opentitan (RV32 only)

`error_abort' on CPU realization exists on following machines:

-   shakti_c (RV64 only)
-   microchip-icicle-kit (RV64 only)

...but since CPU realization on those machine currently never fails
(because they require fixed CPU), I didn't touch those (may be a TODO).




Tsukasa OI (2):
  target/riscv: Make CPU config error handling generous (virt/spike)
  target/riscv: Make CPU config error handling generous
    (sifive_e/u/opentitan)

 hw/riscv/opentitan.c | 2 +-
 hw/riscv/sifive_e.c  | 2 +-
 hw/riscv/sifive_u.c  | 4 ++--
 hw/riscv/spike.c     | 2 +-
 hw/riscv/virt.c      | 2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)


base-commit: 178bacb66d98d9ee7a702b9f2a4dfcd88b72a9ab
-- 
2.34.1