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[PATCH v11 42/77] target/riscv: rvv-1.0: single-width bit shift instruct
From: |
frank . chang |
Subject: |
[PATCH v11 42/77] target/riscv: rvv-1.0: single-width bit shift instructions |
Date: |
Fri, 10 Dec 2021 15:56:28 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 0076ce5a0a..4894212913 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1685,9 +1685,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
-GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli)
-GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri)
-GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari)
+GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_TRUNC_SEW, vsll_vx, shli)
+GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri)
+GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari)
/* Vector Narrowing Integer Right Shift Instructions */
static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
--
2.31.1
- [PATCH v11 33/77] target/riscv: rvv-1.0: element index instruction, (continued)
- [PATCH v11 33/77] target/riscv: rvv-1.0: element index instruction, frank . chang, 2021/12/10
- [PATCH v11 34/77] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/12/10
- [PATCH v11 32/77] target/riscv: rvv-1.0: iota instruction, frank . chang, 2021/12/10
- [PATCH v11 35/77] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2021/12/10
- [PATCH v11 41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2021/12/10
- [PATCH v11 40/77] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2021/12/10
- [PATCH v11 36/77] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2021/12/10
- [PATCH v11 45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2021/12/10
- [PATCH v11 38/77] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2021/12/10
- [PATCH v11 47/77] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2021/12/10
- [PATCH v11 42/77] target/riscv: rvv-1.0: single-width bit shift instructions,
frank . chang <=
- [PATCH v11 43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2021/12/10
- [PATCH v11 37/77] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2021/12/10
- [PATCH v11 39/77] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2021/12/10
- [PATCH v11 44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2021/12/10
- [PATCH v11 50/77] target/riscv: rvv-1.0: slide instructions, frank . chang, 2021/12/10
- [PATCH v11 46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2021/12/10
- [PATCH v11 51/77] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2021/12/10
- [PATCH v11 48/77] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2021/12/10
- [PATCH v11 49/77] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2021/12/10
- [PATCH v11 52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2021/12/10