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[PATCH v11 47/77] target/riscv: rvv-1.0: integer comparison instructions
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From: |
frank . chang |
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Subject: |
[PATCH v11 47/77] target/riscv: rvv-1.0: integer comparison instructions |
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Date: |
Fri, 10 Dec 2021 15:56:33 +0800 |
From: Frank Chang <frank.chang@sifive.com>
* Sign-extend vmselu.vi and vmsgtu.vi immediate values.
* Remove "set tail elements to zeros" as tail elements can be unchanged
for either VTA to have undisturbed or agnostic setting.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c | 9 ---------
2 files changed, 2 insertions(+), 11 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index ed4554b6a1..804f423d5b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1809,9 +1809,9 @@ GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmseq_vi, IMM_SX, vmseq_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmsne_vi, IMM_SX, vmsne_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsleu_vi, IMM_ZX, vmsleu_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsleu_vi, IMM_SX, vmsleu_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmsle_vi, IMM_SX, vmsle_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsgtu_vi, IMM_ZX, vmsgtu_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsgtu_vi, IMM_SX, vmsgtu_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmsgt_vi, IMM_SX, vmsgt_vx, opivx_cmp_check)
/* Vector Integer Min/Max Instructions */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e885d4d353..277a5e4120 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1190,8 +1190,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_max_elems(desc, \
- ctzl(sizeof(ETYPE))); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1202,9 +1200,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
} \
vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
}
GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ)
@@ -1243,7 +1238,6 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1254,9 +1248,6 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
}
GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ)
--
2.31.1
- [PATCH v11 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions, (continued)
- [PATCH v11 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2021/12/10
- [PATCH v11 33/77] target/riscv: rvv-1.0: element index instruction, frank . chang, 2021/12/10
- [PATCH v11 34/77] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/12/10
- [PATCH v11 32/77] target/riscv: rvv-1.0: iota instruction, frank . chang, 2021/12/10
- [PATCH v11 35/77] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2021/12/10
- [PATCH v11 41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2021/12/10
- [PATCH v11 40/77] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2021/12/10
- [PATCH v11 36/77] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2021/12/10
- [PATCH v11 45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2021/12/10
- [PATCH v11 38/77] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2021/12/10
- [PATCH v11 47/77] target/riscv: rvv-1.0: integer comparison instructions,
frank . chang <=
- [PATCH v11 42/77] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2021/12/10
- [PATCH v11 43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2021/12/10
- [PATCH v11 37/77] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2021/12/10
- [PATCH v11 39/77] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2021/12/10
- [PATCH v11 44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2021/12/10
- [PATCH v11 50/77] target/riscv: rvv-1.0: slide instructions, frank . chang, 2021/12/10
- [PATCH v11 46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2021/12/10
- [PATCH v11 51/77] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2021/12/10
- [PATCH v11 48/77] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2021/12/10
- [PATCH v11 49/77] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2021/12/10