[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v11 39/77] target/riscv: rvv-1.0: whole register move instruction
From: |
frank . chang |
Subject: |
[PATCH v11 39/77] target/riscv: rvv-1.0: whole register move instructions |
Date: |
Fri, 10 Dec 2021 15:56:25 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vmv1r.v
* vmv2r.v
* vmv4r.v
* vmv8r.v
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvv.c.inc | 25 +++++++++++++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ab5fdbf9be..06a8076311 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -650,6 +650,10 @@ vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111
@r_vm
vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
+vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
+vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
+vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
+vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 89f88a0ea7..91e7c14ec4 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3259,3 +3259,28 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
}
return false;
}
+
+/*
+ * Whole Vector Register Move Instructions ignore vtype and vl setting.
+ * Thus, we don't need to check vill bit. (Section 16.6)
+ */
+#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
+static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
+{ \
+ if (require_rvv(s) && \
+ QEMU_IS_ALIGNED(a->rd, LEN) && \
+ QEMU_IS_ALIGNED(a->rs2, LEN)) { \
+ /* EEW = 8 */ \
+ tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \
+ vreg_ofs(s, a->rs2), \
+ s->vlen / 8 * LEN, s->vlen / 8 * LEN); \
+ mark_vs_dirty(s); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
+GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
+GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
+GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
--
2.31.1
- [PATCH v11 35/77] target/riscv: rvv-1.0: register gather instructions, (continued)
- [PATCH v11 35/77] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2021/12/10
- [PATCH v11 41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2021/12/10
- [PATCH v11 40/77] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2021/12/10
- [PATCH v11 36/77] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2021/12/10
- [PATCH v11 45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2021/12/10
- [PATCH v11 38/77] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2021/12/10
- [PATCH v11 47/77] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2021/12/10
- [PATCH v11 42/77] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2021/12/10
- [PATCH v11 43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2021/12/10
- [PATCH v11 37/77] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2021/12/10
- [PATCH v11 39/77] target/riscv: rvv-1.0: whole register move instructions,
frank . chang <=
- [PATCH v11 44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2021/12/10
- [PATCH v11 50/77] target/riscv: rvv-1.0: slide instructions, frank . chang, 2021/12/10
- [PATCH v11 46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2021/12/10
- [PATCH v11 51/77] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2021/12/10
- [PATCH v11 48/77] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2021/12/10
- [PATCH v11 49/77] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2021/12/10
- [PATCH v11 52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2021/12/10
- [PATCH v11 53/77] target/riscv: rvv-1.0: single-width floating-point reduction, frank . chang, 2021/12/10
- [PATCH v11 54/77] target/riscv: rvv-1.0: widening floating-point reduction instructions, frank . chang, 2021/12/10
- [PATCH v11 55/77] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 2021/12/10