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[PATCH 6/7] target/riscv: Enable the Hypervisor extension by default
From: |
Alistair Francis |
Subject: |
[PATCH 6/7] target/riscv: Enable the Hypervisor extension by default |
Date: |
Wed, 8 Dec 2021 16:42:51 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
Let's enable the Hypervisor extension by default. This doesn't affect
named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the
Hypervisor extensions by default for the virt machine.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1edb2771b4..013a8760b5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -626,7 +626,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
- DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false),
+ DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
--
2.31.1
- [PATCH 0/7] A collection of RISC-V cleanups and improvements, Alistair Francis, 2021/12/08
- [PATCH 2/7] hw/intc: sifive_plic: Cleanup the write function, Alistair Francis, 2021/12/08
- [PATCH 1/7] hw/intc: sifive_plic: Add a reset function, Alistair Francis, 2021/12/08
- [PATCH 3/7] hw/intc: sifive_plic: Cleanup the read function, Alistair Francis, 2021/12/08
- [PATCH 4/7] hw/intc: sifive_plic: Cleanup remaining functions, Alistair Francis, 2021/12/08
- [PATCH 5/7] target/riscv: Mark the Hypervisor extension as non experimental, Alistair Francis, 2021/12/08
- [PATCH 6/7] target/riscv: Enable the Hypervisor extension by default,
Alistair Francis <=
- [PATCH 7/7] hw/riscv: Use error_fatal for SoC realisation, Alistair Francis, 2021/12/08