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[PATCH 0/7] A collection of RISC-V cleanups and improvements
From: |
Alistair Francis |
Subject: |
[PATCH 0/7] A collection of RISC-V cleanups and improvements |
Date: |
Wed, 8 Dec 2021 16:42:45 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
This is a few patches to cleanup some RISC-V hardware and mark the
Hyperisor extension as non experimental.
Alistair Francis (7):
hw/intc: sifive_plic: Add a reset function
hw/intc: sifive_plic: Cleanup the write function
hw/intc: sifive_plic: Cleanup the read function
hw/intc: sifive_plic: Cleanup remaining functions
target/riscv: Mark the Hypervisor extension as non experimental
target/riscv: Enable the Hypervisor extension by default
hw/riscv: Use error_fatal for SoC realisation
hw/intc/sifive_plic.c | 254 +++++++++++--------------------------
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/opentitan.c | 2 +-
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
target/riscv/cpu.c | 2 +-
6 files changed, 81 insertions(+), 183 deletions(-)
--
2.31.1
- [PATCH 0/7] A collection of RISC-V cleanups and improvements,
Alistair Francis <=
- [PATCH 2/7] hw/intc: sifive_plic: Cleanup the write function, Alistair Francis, 2021/12/08
- [PATCH 1/7] hw/intc: sifive_plic: Add a reset function, Alistair Francis, 2021/12/08
- [PATCH 3/7] hw/intc: sifive_plic: Cleanup the read function, Alistair Francis, 2021/12/08
- [PATCH 4/7] hw/intc: sifive_plic: Cleanup remaining functions, Alistair Francis, 2021/12/08
- [PATCH 5/7] target/riscv: Mark the Hypervisor extension as non experimental, Alistair Francis, 2021/12/08
- [PATCH 6/7] target/riscv: Enable the Hypervisor extension by default, Alistair Francis, 2021/12/08
- [PATCH 7/7] hw/riscv: Use error_fatal for SoC realisation, Alistair Francis, 2021/12/08