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[PATCH 5/7] target/riscv: Mark the Hypervisor extension as non experimen
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From: |
Alistair Francis |
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Subject: |
[PATCH 5/7] target/riscv: Mark the Hypervisor extension as non experimental |
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Date: |
Wed, 8 Dec 2021 16:42:50 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
The Hypervisor spec is now frozen, so remove the experimental tag.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f812998123..1edb2771b4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -626,6 +626,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
+ DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
@@ -639,7 +640,6 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
- DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
--
2.31.1
- [PATCH 0/7] A collection of RISC-V cleanups and improvements, Alistair Francis, 2021/12/08
- [PATCH 2/7] hw/intc: sifive_plic: Cleanup the write function, Alistair Francis, 2021/12/08
- [PATCH 1/7] hw/intc: sifive_plic: Add a reset function, Alistair Francis, 2021/12/08
- [PATCH 3/7] hw/intc: sifive_plic: Cleanup the read function, Alistair Francis, 2021/12/08
- [PATCH 4/7] hw/intc: sifive_plic: Cleanup remaining functions, Alistair Francis, 2021/12/08
- [PATCH 5/7] target/riscv: Mark the Hypervisor extension as non experimental,
Alistair Francis <=
- [PATCH 6/7] target/riscv: Enable the Hypervisor extension by default, Alistair Francis, 2021/12/08
- [PATCH 7/7] hw/riscv: Use error_fatal for SoC realisation, Alistair Francis, 2021/12/08