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Re: [Qemu-riscv] [Qemu-devel] [PATCH 09/28] riscv: sifive_u: Update UART
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From: |
Alistair Francis |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH 09/28] riscv: sifive_u: Update UART base addresses |
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Date: |
Mon, 5 Aug 2019 17:19:16 -0700 |
On Mon, Aug 5, 2019 at 9:05 AM Bin Meng <address@hidden> wrote:
>
> This updates the UART base address to match the hardware.
>
> Signed-off-by: Bin Meng <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index b235f29..9f05e09 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -60,8 +60,8 @@ static const struct MemmapEntry {
> [SIFIVE_U_MROM] = { 0x1000, 0x11000 },
> [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
> [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
> - [SIFIVE_U_UART0] = { 0x10013000, 0x1000 },
> - [SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
> + [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
> + [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
> [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
> };
> --
> 2.7.4
>
>
- Re: [Qemu-riscv] [Qemu-devel] [PATCH 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, (continued)
- [Qemu-riscv] [PATCH 05/28] riscv: hart: Support heterogeneous harts population, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 04/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 09/28] riscv: sifive_u: Update UART base addresses, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 13/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 08/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 26/28] riscv: hw: Update PLIC device tree, Bin Meng, 2019/08/05