[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-riscv] [PATCH 13/28] riscv: sifive_e: prci: Update the PRCI regist
From: |
Bin Meng |
Subject: |
[Qemu-riscv] [PATCH 13/28] riscv: sifive_e: prci: Update the PRCI register block size |
Date: |
Mon, 5 Aug 2019 09:00:08 -0700 |
Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.
Signed-off-by: Bin Meng <address@hidden>
---
hw/riscv/sifive_e_prci.c | 2 +-
include/hw/riscv/sifive_e_prci.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c
index c906f11..4cbce48 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -85,7 +85,7 @@ static void sifive_prci_init(Object *obj)
SiFivePRCIState *s = SIFIVE_E_PRCI(obj);
memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s,
- TYPE_SIFIVE_E_PRCI, 0x8000);
+ TYPE_SIFIVE_E_PRCI, SIFIVE_E_PRCI_REG_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_prci.h
index 7932fe7..81e506b 100644
--- a/include/hw/riscv/sifive_e_prci.h
+++ b/include/hw/riscv/sifive_e_prci.h
@@ -47,6 +47,8 @@ enum {
SIFIVE_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
};
+#define SIFIVE_E_PRCI_REG_SIZE 0x1000
+
#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci"
#define SIFIVE_E_PRCI(obj) \
--
2.7.4
- [Qemu-riscv] [PATCH 05/28] riscv: hart: Support heterogeneous harts population, (continued)
- [Qemu-riscv] [PATCH 05/28] riscv: hart: Support heterogeneous harts population, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 04/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 09/28] riscv: sifive_u: Update UART base addresses, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 13/28] riscv: sifive_e: prci: Update the PRCI register block size,
Bin Meng <=
- [Qemu-riscv] [PATCH 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 08/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 26/28] riscv: hw: Update PLIC device tree, Bin Meng, 2019/08/05