Re: [Qemu-riscv] [PATCH 07/28] riscv: sifive

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Re: [Qemu-riscv] [PATCH 07/28] riscv: sifive_u: Set the minimum number o

From:	Jonathan Behrens
Subject:	Re: [Qemu-riscv] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2
Date:	Mon, 5 Aug 2019 12:41:47 -0400

I'm not familiar with QEMU conventions on this, but would it make sense to require having exactly 5 CPUs to match the real board?

Jonathan

On Mon, Aug 5, 2019 at 12:05 PM Bin Meng <address@hidden> wrote:

It is not useful if we only have one management CPU.

Signed-off-by: Bin Meng <address@hidden>
---

hw/riscv/sifive_u.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 08d406f..206eccc 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -428,6 +428,8 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
* management CPU.
*/
mc->max_cpus = 5;
+ /* It is not useful if we only have one management CPU */
+ mc->min_cpus = 2;
}

DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
--
2.7.4

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[Qemu-riscv] [PATCH 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 01/28] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/08/05
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH 01/28] riscv: hw: Remove superfluous "linux, phandle" property, Alistair Francis, 2019/08/05
- [Qemu-riscv] [PATCH 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/05
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Alistair Francis, 2019/08/05
- [Qemu-riscv] [PATCH 05/28] riscv: hart: Support heterogeneous harts population, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/05
  - Re: [Qemu-riscv] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, Jonathan Behrens <=
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, Alistair Francis, 2019/08/05
- [Qemu-riscv] [PATCH 04/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/05
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Alistair Francis, 2019/08/05
- [Qemu-riscv] [PATCH 09/28] riscv: sifive_u: Update UART base addresses, Bin Meng, 2019/08/05
  - Re: [Qemu-riscv] [PATCH 09/28] riscv: sifive_u: Update UART base addresses, Jonathan Behrens, 2019/08/05
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH 09/28] riscv: sifive_u: Update UART base addresses, Alistair Francis, 2019/08/05
- [Qemu-riscv] [PATCH 13/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 08/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/05

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