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[Qemu-riscv] [PATCH 23/28] riscv: sifive: Move sifive_mmio_emulate() to
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From: |
Bin Meng |
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Subject: |
[Qemu-riscv] [PATCH 23/28] riscv: sifive: Move sifive_mmio_emulate() to a common place |
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Date: |
Mon, 5 Aug 2019 09:00:18 -0700 |
sifive_mmio_emulate() is currently only used in the sifive_e machine
codes. It can be helpful for other machines as well.
Change it to an inline routine and move it to sifive_cpu.h, so that
other machines like sifive_u can use it.
Signed-off-by: Bin Meng <address@hidden>
---
hw/riscv/sifive_e.c | 8 --------
include/hw/riscv/sifive_cpu.h | 10 +++++++++-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 2d67670..7e0fe7b 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -74,14 +74,6 @@ static const struct MemmapEntry {
[SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
};
-static void sifive_mmio_emulate(MemoryRegion *parent, const char *name,
- uintptr_t offset, uintptr_t length)
-{
- MemoryRegion *mock_mmio = g_new(MemoryRegion, 1);
- memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal);
- memory_region_add_subregion(parent, offset, mock_mmio);
-}
-
static void riscv_sifive_e_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_e_memmap;
diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h
index 1367996..897b8f8 100644
--- a/include/hw/riscv/sifive_cpu.h
+++ b/include/hw/riscv/sifive_cpu.h
@@ -1,5 +1,5 @@
/*
- * SiFive CPU types
+ * SiFive CPU types and common utilities
*
* Copyright (c) 2017 SiFive, Inc.
* Copyright (c) 2019 Bin Meng <address@hidden>
@@ -28,4 +28,12 @@
#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
#endif
+static inline void sifive_mmio_emulate(MemoryRegion *parent, const char *name,
+ uintptr_t offset, uintptr_t length)
+{
+ MemoryRegion *mock_mmio = g_new(MemoryRegion, 1);
+ memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal);
+ memory_region_add_subregion(parent, offset, mock_mmio);
+}
+
#endif /* HW_SIFIVE_CPU_H */
--
2.7.4
- [Qemu-riscv] [PATCH 14/28] riscv: sifive: Implement PRCI model for FU540, (continued)
- [Qemu-riscv] [PATCH 14/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 27/28] riscv: virt: Change create_fdt() to return void, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 21/28] riscv: sifive_u: Update UART and ethernet node clock properties, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 22/28] riscv: sifive_u: Generate an aliases node in the device tree, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 16/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 17/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 25/28] riscv: sifive_u: Support loading initramfs, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 23/28] riscv: sifive: Move sifive_mmio_emulate() to a common place,
Bin Meng <=
- [Qemu-riscv] [PATCH 24/28] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 28/28] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/05