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[Qemu-riscv] [PATCH 22/28] riscv: sifive_u: Generate an aliases node in
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From: |
Bin Meng |
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Subject: |
[Qemu-riscv] [PATCH 22/28] riscv: sifive_u: Generate an aliases node in the device tree |
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Date: |
Mon, 5 Aug 2019 09:00:17 -0700 |
The Linux kernel SiFive UART driver expects an aliases node to be
present in the device tree, from which the driver extracts the port
number from "serial#" in the aliases node.
Signed-off-by: Bin Meng <address@hidden>
---
hw/riscv/sifive_u.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 061d6d4..9945b82 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -283,6 +283,8 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
if (cmdline) {
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
}
+ qemu_fdt_add_subnode(fdt, "/aliases");
+ qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
g_free(nodename);
}
--
2.7.4
- [Qemu-riscv] [PATCH 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, (continued)
- [Qemu-riscv] [PATCH 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 26/28] riscv: hw: Update PLIC device tree, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 14/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 27/28] riscv: virt: Change create_fdt() to return void, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 21/28] riscv: sifive_u: Update UART and ethernet node clock properties, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 22/28] riscv: sifive_u: Generate an aliases node in the device tree,
Bin Meng <=
- [Qemu-riscv] [PATCH 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 16/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 17/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 25/28] riscv: sifive_u: Support loading initramfs, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 23/28] riscv: sifive: Move sifive_mmio_emulate() to a common place, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 24/28] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 28/28] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/05