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[Qemu-riscv] [PATCH 17/28] riscv: sifive_u: Change UART node name in dev
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From: |
Bin Meng |
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Subject: |
[Qemu-riscv] [PATCH 17/28] riscv: sifive_u: Change UART node name in device tree |
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Date: |
Mon, 5 Aug 2019 09:00:12 -0700 |
OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating
chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will
use this information to locate the serial node and probe its driver.
However currently we generate the UART node name as "/soc/uart@...",
causing U-Boot fail to find the serial node in DT.
Signed-off-by: Bin Meng <address@hidden>
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 20dee52..8044166 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -273,7 +273,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
g_free(nodename);
- nodename = g_strdup_printf("/soc/uart@%lx",
+ nodename = g_strdup_printf("/soc/serial@%lx",
(long)memmap[SIFIVE_U_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
--
2.7.4
- Re: [Qemu-riscv] [Qemu-devel] [PATCH 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, (continued)
- [Qemu-riscv] [PATCH 26/28] riscv: hw: Update PLIC device tree, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 14/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 27/28] riscv: virt: Change create_fdt() to return void, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 21/28] riscv: sifive_u: Update UART and ethernet node clock properties, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 22/28] riscv: sifive_u: Generate an aliases node in the device tree, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 16/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 17/28] riscv: sifive_u: Change UART node name in device tree,
Bin Meng <=
- [Qemu-riscv] [PATCH 25/28] riscv: sifive_u: Support loading initramfs, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 23/28] riscv: sifive: Move sifive_mmio_emulate() to a common place, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 24/28] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/05
- [Qemu-riscv] [PATCH 28/28] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/05