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[Qemu-riscv] [PATCH v1 6/9] target/riscv: Require either I or E base ext
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From: |
Alistair Francis |
|
Subject: |
[Qemu-riscv] [PATCH v1 6/9] target/riscv: Require either I or E base extension |
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Date: |
Mon, 17 Jun 2019 18:31:16 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a23d83921a..21bfaa9722 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -373,6 +373,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
+ if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
+ error_setg(errp,
+ "Either I or E extension must be set");
+ return;
+ }
+
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
cpu->cfg.ext_a & cpu->cfg.ext_f &
cpu->cfg.ext_d)) {
--
2.22.0
- [Qemu-riscv] [PATCH v1 0/9] Update the RISC-V specification versions, Alistair Francis, 2019/06/17
- [Qemu-riscv] [PATCH v1 2/9] target/riscv: Add the privledge spec version 1.11.0, Alistair Francis, 2019/06/17
- [Qemu-riscv] [PATCH v1 3/9] target/riscv: Comment in the mcountinhibit CSR, Alistair Francis, 2019/06/17
- [Qemu-riscv] [PATCH v1 1/9] target/riscv: Restructure deprecatd CPUs, Alistair Francis, 2019/06/17
- [Qemu-riscv] [PATCH v1 4/9] target/riscv: Set privledge spec 1.11.0 as default, Alistair Francis, 2019/06/17
- [Qemu-riscv] [PATCH v1 5/9] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1, Alistair Francis, 2019/06/17
- [Qemu-riscv] [PATCH v1 6/9] target/riscv: Require either I or E base extension,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 7/9] target/riscv: Remove user version information, Alistair Francis, 2019/06/17
- [Qemu-riscv] [PATCH v1 8/9] target/riscv: Add support for disabling/enabling Counters, Alistair Francis, 2019/06/17
- [Qemu-riscv] [PATCH v1 9/9] target/riscv: Add Zifencei and Zicsr as command line options, Alistair Francis, 2019/06/17
- Re: [Qemu-riscv] [PATCH v1 0/9] Update the RISC-V specification versions, Palmer Dabbelt, 2019/06/19